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A formation technology of ultra-low series resistance CMOS source/drain (S/D) electrodes is developed. The silicide/silicon contact resistivity (Rc) of 8.0×10-10 Ω·cm2 and the electrode's sheet resistance (Rsheet) of less than 5.0 Ω/□ are achieved for both n- and pMOS using W/ErSi2 and W/Pd2Si metal stacked silicide structures. For the first time, FD-SOI CMOS with the developed S/D electrodes was...
We investigated structural and electrical properties of Ge and Si metal oxide semiconductor (MOS) devices with Pt/HfO2 gate stacks. Post-metallization annealing in O2 ambient reduced the accumulation capacitance more significantly in Si devices than in Ge devices due to the increase in the thickness of a low-k interfacial layer in-between the HfO2 film and Si substrate. Ge devices exhibited lower...
A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at Ioff=100 nA/μm with VDD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
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