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High speed and low power SBOX for Advanced Encryption Standard (AES) is proposed in this paper. Composite Galois Field is used in SBOX architecture to reduce size and delay of the circuit. Transmission gate is employed to reduce power consumption of the circuit. The proposed SBOX architecture consumes 186μw at 10MHz. The delay is reduced by 28.1%, and the average power consumption is reduced by 68...
Novel architectures for designing modulo 2n+1 subtractors are introduced, for both the normal and the diminished-one number representation of the operands. Zero-handling is also considered in the diminished-one operand representation case. The modulo 2n+1 subtractors for operands in the normal representation that are proposed are shown to be more efficient in area, delay and power dissipation than...
This paper presents a new study over logics circuit operation in subthreshold and threshold region. CMOS circuit model operation logic will make deep primary reference for this study. This new research presses low voltage features to circuit stated. By using profoundest results of the study, we will develop FFT processor designs as an example of digital wireless circuits. The FFT processor can operate...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
The purpose of this report is to provide the state-of-the-art of high performance arithmetic integrated circuits (ICs). The survey concentrates on arithmetic ICs that are designed to improve execution speed over software techniques, therefore, no calculator chips are surveyed. In order to understand the difficulties encountered in fabricating high speed arithmetic ICs, we start the article with a...
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