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At-speed scan testing for intra-clock and inter-clock transition delay faults in a SOC design with multiple clock domains is an important and challenging issue. Current practice in industry usually applies a test scheme targeted on intra-clock transition fault delay testing (i.e., intra testing). In this paper a test scheme targeting both intra-clock and inter-clock domains for transition delay fault...
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper provides a comprehensive overview of the types and sources of all aspects of process variations in driver -interconnect-load system. The primary sources of manufacturing variation include Deposition, Chemical Mechanical Planarization (CMP), Etching, Resolution Enhancement...
Time budgeting, which assigns timing assertion at block boundary, is a crucial step in hierarchical design. The proportion of high- and low-Vt gates of each block, which determines overall leakage power consumption, is dictated by timing assertion, yet dual-Vt allocation is not taken into account during conventional time budgeting. Bounded potential slack is introduced as a measure of dual-Vt allocation,...
Due to rapidly growing system-on-chip industry, not only the faster units but also smaller area and less power has become a major design constraint for VLSI community. Further, demand for high speed is continuously increasing. In processors, most commonly used arithmetic operation is the addition operation. It is the adder delay that determines the maximum frequency of operation of the chip. Different...
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