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Accurate estimation of delays in Static Timing Analysis (STA) using Non Linear Delay Model (NLDM) based Look Up Table (LUT) is a major challenge in nanometer range VLSI circuits. Issues with NLDM based LUT are mostly due to the arbitrary choice of input signal transition time trin and load capacitance (Cl) and the large number of simulations to be performed for characterizing an entire standard cell...
While scan-based compression is widely utilized in order to alleviate the test time and data volume problems, the overall compression level is dictated not only by the chain to channel ratio but also the ratio of encodable patterns. Aggressively increasing the number of scan chains in an effort to raise the compression levels may reduce the ratio of encodable patterns, degrading the overall compression...
As technology is aggressively scaled, nano-regime VLSI designs are becoming increasingly susceptible to process variations. Unlike pre-silicon optimization, post-silicon techniques can tune the individual die to better meet the power-delay constraints. This paper proposes a variation-aware methodology for the simultaneous gate sizing and clustering for post-silicon tuning with adaptive body biasing...
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