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A fast-lock all-digital register-controlled delay-locked loop (RCDLL) with wide-range duty cycle adjuster is presented. The architecture of the proposed fast-lock RCDLL uses the initial delay monitor without the delay line, which shares with the register controlled delay line for high accuracy of initial delay. Also, the duty cycle corrector of the DLL has achieved wide correction range to a small...
Dynamic Power Management (DPM) is a technique to reduce the power consumption of an electronic system by selectively shutting down idle components. In this paper, a DPM methodology is proposed for managing the power consumption of System on Chip (SoC) in batteryless TPMS. The main circuit adopts three power regulators to supply the IP cores (CMOS Temperature Sensor + A/D + MCU + 433MHz Data Transmitter)...
Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is a promising approach to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between...
We have developed a voltage control scheme to reduce control time using a delay monitor and step-by-step supply-voltage control. With this scheme, voltage control steps are adaptively controlled, and there are temporary overshoots in the reference voltage. Experimental results with a 65-nm CMOS device indicate that the adaptive voltage control steps successfully reduce the voltage control time by...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
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