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In this paper, in order to reduce discretization errors of dynamics with variable structures (VS), we propose an improved digital integrator. Use of Richardson extrapolation (RE) and fractional delay (FD) can improve Euler integrator, so we can obtain an improved integrator. However, Euler integrator using RE and FD directly has an infinite gain at a Nyquist frequency, and it is unsuitable for integrations...
This paper describes a design for a variable fractional delay (VFD) FIR filter implemented on reconfigurable hardware. Fractionally delayed signals are required for several audio-based applications, including echo cancellation and musical signal analysis. Traditionally, VFD FIR filters are implemented using a complex, fixed structure based upon the order of the filter. This fixed structure restricts...
The importance of processing of digital signals has dramatically increased due to widespread use of digital systems. A new FPGA based technique for processing of two digital signals to generate a new signal as a product of two signals is presented. The technique is based upon the use of orthogonal functions to describe digital signals.
Previously, a two-step approach to perform the cyclic redundancy check (CRC) computation in hardware was presented. In that approach, an architecture is constructed from a suitable multiple polynomial for a fixed generator polynomial and input size. In this paper, we revisit the two-step approach and suggest a modification to its architecture. First, we propose retiming the second step to the delay...
A reconfigurable architecture for efficient computation of several elementary functions, in double precision floating-point format, is presented in this paper. The main idea is to tailor the computation method towards FPGA resources of Virtex-II circuits to increase the execution performances of these functions. Our method employs a piecewise minimax approximation and look-up tables. To achieve a...
A reconfigurable architecture for efficient computation of several elementary functions, in double precision floating-point format, is presented in this paper. The main idea is to tailor the computation method towards FPGA resources of Virtex-II circuits to increase the execution performances of these functions. Our method employs a piecewise minimax approximation and look-up tables. To attain a precision...
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