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A reliability study of high-k/metal gate stack transistors with a sub-nanometer equivalent oxide thickness (EOT) and engineered interfacial layer (IL) having a k value higher than that of conventional SiO2 thin film is reported. The mobility reduction in these ldquozerordquo SiOx IL devices exhibits a consistent trend of a positive charge buildup and increased interface state density associated with...
In this work we propose a unified model for the low-field effective electron mobility in SOI and DG-MOSFETs with ultrathin SiO2/HfO2 gate stacks, different substrate and channel orientations and uniaxial stress conditions.The model accounts for quantum-confinement effects in the MOSFET channel. Next, we apply this mobility model to a 1D quantum drift-diffusion (QDD) transport model in order to investigate...
Damascene gate process enhances the drivability in shorter gate length region, as compared to conventional gate 1st process for pFETs with compressive stress SiN liner and embedded SiGe. The origin of the gate length effect is investigated for the first time by using the UV-Raman spectroscopy. Moreover, the relationship between channel strain and gate width for damascene gate pFETs is analyzed and...
Compressively strained Ge long channel ring-type pMOSFETs with high-kappa Si/SiO2/HfO2/TiN gate stacks are fabricated on Si0.2Ge0.8 virtual substrates. Effective oxide thickness is approximately 1.4 nm with low gate leakage current. A peak hole mobility of 640 cm2/ Vldrs and up to a four times enhancement over the Si/SiO2 universal curve are observed. Parasitic conduction within the Si-cap layers...
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