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This brief introduces a simple circuit solution to secure loop stability of an analog-domain fast-frequency offset cancellation loop (OCL). The OCL is composed of a low-IF receiver, phase-domain frequency offset detector (OD), and fractional-N phase-locked loop (PLL). Since the OCL uses a phase-domain OD, a stability concern is essentially needed for its practical use. From the frequency-domain analysis,...
A frequency synthesizer combining offset phase-locked loop (OPLL) and direct-digital synthesis (DDS) is presented in this paper. DDS is for channel selection as it inherits fast settling and fine resolution characteristics. OPLL structure helps to lower the DDS operation speed thus reduce the power dissipation. Compared with the conventional PLL, this structure relieves the tradeoff between loop bandwidth...
A 0.18 /spl mu/m CMOS IEEE 802.11b SoC integrated all the radio building blocks including the PA, the PLL loop filter, and the antenna switch, as well as the complete physical layer and the MAC sections. At 2.4 GHz, it dissipates 165 mW in the receive-mode and 360 mW in the transmit-mode from a 1.8 V supply. The receiver achieves a typical NF of 6 dB, and -88 dBm sensitivity at 11 Mbit/s rate. The...
A CMOS current steering 12b 500MS/s 216mW DAC without any additional circuitry to remove errors introduced during the conversion process has >70dB SFDR up to 120MHz above the Nyquist band. This is comparable to state-of-the-art performance requiring additional circuitry, and better than any design without additional circuitry
A 0.18 /spl mu/m CMOS single-chip fully integrated quad-band GSM/GPRS transceiver is presented. The low-IF receive section achieves -110dBm sensitivity at the antenna and -15dBm IIP3. The offset-frequency PLL transmitter achieves 1.2/spl deg/ rms phase noise, -65dBc modulation mask at 400kHz, and -165dBc/Hz noise at 20MHz. The chip occupies 17mm/sup 2/ and dissipates 95mA/112mA in receive/transmit...
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