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Prospects of velocity enhancement as the main driver of performance scaling in future CMOS are examined. Limits of velocity enhancement in uniaxially strained Si are first presented and then outlooks of novel channel materials such as Ge and III-V semiconductors are discussed. Finally, characteristics of performance scaling under power dissipation constraints are studied.
There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.
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