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Hybrid CMOS-SET architectures, which combine the merits of CMOS and SET (single-electron tunneling) devices, promise to be a practical implementation for nanometer-scale circuit design. In this work we propose two binary full adders using hybrid CMOS-SET parallel architectures, which take advantage of the Coulomb oscillation with SET devices in order to improve the circuit area, power consumption...
In this paper the effect of source parasitic capacitances on phase noise in CMOS LC oscillators is studied. A new model for the noise of differential pair transistors in triode region is presented. Based on the given model, the dependency of the phase noise on differential pair transistors sizing is introduced and the function of the used LC noise filter in the tail is analytically investigated. The...
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