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The objective of this paper is to investigate the design and implementation of driver circuits and find out the best fit driver for controlling power transistors. We implemented three drivers in 65 nanometer CMOS technology, and the design criteria for these drivers were mainly focused on reducing the power consumption, which is one of the most important specifications when designing portable consumer...
This paper deals with the design, the realization and the characterization of an integrated converter for low voltage and low power, isolated applications (3.3 V, 1 W). It is based on the association of two generic silicon dies performing DC to AC and AC to DC operations. The power dies are designed in CMOS technology and operate at high frequency (1 MHz) and high efficiency. This high power density...
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
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