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We report an original Dual Channel-On-Insulator (DCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/SiGe/(s)SOI with a TiN/HfO2 gate stack (EOT=1.15 nm) and down to 40 nm gate lengths. We demonstrate for the first time large gains for transconductance (up to +125%) and mobility (+100%) even for short channel pFETs. This enables us to improve the ON(OFF) pFETs trade-off...
In this work, 3D monolithic cells have been demonstrated, featuring the first perfectly crystalline upper active layer thanks to wafer bonding. The low temperature process (<600degC) of the top GeOI and SOI MOSFETs leads to well behaved characteristics and allows preservation of bottom FETs performance. The benefit of the decreased process temperature is highlighted by improved short channel effect...
Logic CMOS technology roadmap for `22 nm and beyond' is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The predicted trend has been amended to be less aggressive from the ITRS 2008-Update, resulting in the delay in the gate-length shrinkage...
Active-matrix organic light-emitting-diode (AMOLED) displays based on amorphous hydrogenated silicon (a-Si:H) thin-film transistors (TFTs) are the state of the art in display technology, owing to the feasilibility of low-cost fabrication and accessability to well-established TFT-LCD fabrication. While the a-Si:H TFT offers excellent matching of device properties over large areas, it suffers from a...
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