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The effects of dielectric slots on Cu/Low-k interconnects reliability were studied. Dielectric slots were proven to be effective in suppressing stress-induced void failure but their impact on EM reliability was found to be minimal. Physical failure analysis and finite element simulations were used to explain the possible mechanisms associated to the different effects of dielectric slots on Cu/low-k...
Upstream electromigration (EM) study was performed on different multiple via structures with different Cu line dimensions. EM performance was found to be dependent on both via layout and Cu line dimension. Failure analysis showed different EM failure modes and diffusion paths on these structures with their different grain morphology. Finite element analysis is applied to find out the current density...
Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is used to optimize the interconnect scheme from a packaging reliability point of view. Factors including top metal (or SiO2) thickness, passivation dielectric...
The temperature dependent driving force for stress induced voiding of Cu dual damascene interconnects has been studied using finite element modeling. Both 2D axisymmetric and 3D models have been investigated. Interconnect test structures have been simulated at temperatures ranging from 25 to 300degC and a stress free temperature for the structure is demonstrated, consistent with analytical modeling...
We have conducted stress-induced voiding (SIV) experiments on Cu/low-k interconnect with different geometries of via structures and upper metal cap layers to evaluate their reliability impact. We showed the cap layer of upper metal had strong effect on the SIV performance. The degrees of such SIV degradations varied with different via structure geometries. A 3D Finite Element Analysis (FEA) is applied...
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