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Part II of this paper series focuses on automation of the extended proof-carrying hardware intellectual property (PCHIP) framework for data secrecy protection in third-party IPs, which was presented in part I. Specifically, we introduce: 1) VeriCoq-IFT, an automated PCHIP framework for information flow policies and 2) VeriCoq-H, a hierarchy-preserving Verilog-to-Coq converter. VeriCoq-IFT aims to:...
Open source hardware projects are becoming more and more common. OpenRISC SOC, one of the prominent of these projects, has become quite popular with the support of volunteer developers. In this work, we have demonstrated the design of an DES (Data Encryption Standard) based system, that can be used in security applications, on ORPSoC-v2 (Openrisc Reference Platform System-on-Chip). Additionally, we...
Authenticated ciphers are cryptographic transformations which combine the functionality of confidentiality, integrity, and authentication. This research uses register transfer-level (RTL) design to describe selected authenticated ciphers using a hardware description language (HDL), verifies their proper operation through functional simulation, and implements them on target FPGAs -- the Xilinx Virtex-6...
This paper investigates the state of the current high-level synthesis (HLS) tools by using Xilinx Vivado HLS for designing a cryptographic module based on Advanced Encryption Standard. The obtained results are compared with the results for the hand-written Register-Transfer Level (RTL) VHDL code to determine the suitability of the HLS-based approach for implementing cryptographic algorithms in hardware...
Hardware efficient stream ciphers and hash functions are widely used in cryptographic applications. The one-wayness and low hardware complexity of hash function make it a good candidate for authentication operation of crypto-systems. On the other hand, stream ciphers are being widely used in the domain of cryptology. Generally, these stream ciphers use static key stream for the crypto process. In...
Verification is a challenge that consumes an increasing part of the design time in the design flow of modern hardware systems. We propose an Assertion Based Verification (ABV) method with embedding synthesizable clock-accurate assertion checkers in higher levels of abstraction in the design flow. Both the Design Under Verification (DUV) and its synthesizable assertion checkers are described using...
The intension of this work is to design ASIC (Application Specific Integrated Circuit) for LFSRs (Linear feedback shift register) used in cryptography systems.(Stream ciphering). Presently FPGAs (Field Programmable Gate Array) and Processors are used for this purpose which have speed limitations. Since FPGAs have general structure and implementing LFSRs in FPGAs are unable to achieve the required...
With the development of networking technology, Hardware encryption technology will become an irreplaceable safety technology. In this paper, a method of AES encryption and decryption algorithm implemented on the same FPGA is presented, where a 128-bit key size mode is implemented, Modelsim simulation test results are demonstrated, the correctness of logic function of the system is verified, and system...
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