As operation frequencies and integration densities of modern very large-scale integration (VLSI) circuits increase while device sizes shrink, the quest for high-speed VLSI applications has highlighted the negligible effects of interconnects. It is important to minimize the interconnect wire lengths during VLSI physical design stage. This paper focuses on the minimization process of the total wire length after placement, that is, macro-cell orientation. A novel evolutionary neural network approach based on the concept of evolutionary programming (EPENN) is proposed to address this combinatorial optimization problem. Numerical experiments and simulation results have shown that the presented approach can obtain high quality solutions with low computational complexity.