In this study curtailing of idle current in 1T1C and 1T1M DRAM cells by increasing threshold voltage during holding state is analyzed. This is attained by connecting the bulk to source in the active phases and pulling it below source potential throughout the holding phase. The proposed technique leads to body effect which affects the threshold voltage improving leakage current. The 1T1C and 1T1M discussed in this paper are volatile and non-volatile (memristor based) respectively. Memory design is fast becoming the pacemaker in the modern technology design which now requires DRAM cells with prolonged holding period and low idle power hence the need for lowering the leakage current. The dynamic nature of the 1T1C is due to charge leakage and the leakage current flowing through the 1T1M cell affects mem-resistance all this leading to state distortion. Idle current has of-late become one of the major contributors of power in large memory arrays in which in-active periods now dominates active period and by this technique idle power is reduced in both volatile and non-volatile cells. The proposed technique was implemented and simulations were done at different voltage levels at 45 nm technology. The method improved the leakage current, holding time and leakage power but at the expense of area and writing power.