In this paper, a low-power high-speed hybrid full adder cell is proposed, which is implemented based on two-input multi-threshold $$({V}_{\mathrm{t}})$$ (Vt) XNOR circuit and transmission gate multiplexers. In order to implement this circuit, carbon nanotube field-effect transistors are utilized. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects of digital circuits: power, delay and power–delay product. The results are presented and confirm the superiority of the proposed cell with the previously reported one in different voltage levels, load conditions, temperatures and robustness in large structures and against process variations.