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Today’s design community need tools that address early power estimation, making it possible to find the optimal design trade-offs without respinning to explore the whole chip. Several approaches based on a fast (coarse) logic synthesis step, in order to analyze power on the mapped gate-level netlist and then create suitable power models have been published in the last years. In this paper we present...
Most power macromodels for RTL datapath modules are both data-dependent and activity-sensitive, that is, they model power in terms of some activity measure of the data inputs of the module. These models have proved to be quite accurate for most combinational RTL datapath macros (such as adders and multipliers), as well as for storage units (such as registers). They tend to become inadequate for RTL...
An approach for power modelling of parameterized, technology independent design components (firm-macros) is presented. Executable simulation models in form of C++ classes are generated by a systematic procedure that is based on statistical modelling and table look-up techniques. In contrast to other table look-up based approaches the proposed model separately handles the inputs of a component, and...
Power dissipation due to the steering logic, that is, the multiplexer network and the interconnect, can usually account for a significant fraction of the total power budget. In this work, we present RTL power models for these two types of architectural elements. The multiplexer model leverages existing scalable models, and can be used for special complex types with re-configurable numbers of data...
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