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Silicon deep reactive ion etching (DRIE) is having a great effect on micro-electro-mechanical systems technology (MEMS) and quite recently also on memory devices and through-silicon via (TSV) etch applications. Nowadays, it is an established fabrication process within the MEMS field. The basic technology was originally developed at Bosch in the early 1990s. At that time, classical wet etching in KOH...
Three-dimensional (3D) integration complements semiconductor scaling in enabling higher integration density as well as heterogeneous technology integration. Through 3D chip stacking it is possible to extend the number of functions per 3D chip well beyond the near-term capabilities of traditional scaling. The 3D strata may be realised using advanced CMOS technology nodes but may also exploit a wide...
Various generic methods for the three-dimensional (3D) integration of integrated circuits (ICs) are discussed. All these methods rely on ultra-thin chips. Wafer-to-wafer bonding, chip-to-wafer bonding, multichip-to-wafer bonding and reconfigured wafer-to-wafer bonding are described and compared. Several test chips fabricated by that use some of those concepts are briefly mentioned. Finally, specific...
This chapter describes the necessity that carrier techniques be developed for thin wafer handling and processing. After an explanation on the main requirements for handle substrate techniques, we give an overview on the following temporary bonding techniques and mechanisms: thermoplastic adhesives, release layers, soluble glues, reversible tapes, mechanical debonding and electrostatic bonding. Finally,...
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