The previous chapters have introduced a multidimensional data flow model of computation that can represent complex image processing applications including (i) out-of-order communication, (ii) sliding windows, (iii) parallel data access, and (iv) control flow. Furthermore, it has been shown how it helps to verify applications on a high level of abstraction assuring bounded memory execution and how required communication buffer sizes can be determined automatically either by simulation or by polyhedral buffer analysis. Corresponding tradeoffs between the required computation logic of the used hardware accelerators and the communication buffers by which they are interconnected have been evaluated in Section 7.7.