Input queued and combined input/output queued switchingarc hitectures must be controlled by a schedulingalg orithm, which solves contention in the transfer of data units to switch outputs. We consider the case of packet switches (or routers), i.e., devices operatingon variable-size data units at their interfaces, assuming that they internally operate on fixed-size data units, and we propose novel extensions of known schedulinga lgorithms for input queued and combined input/output queued architectures. We show by simulation that such architectures can provide performance advantages over traditional output queued architectures.