Neural network is employed to construct the power macromodel of complementary metal-oxide-semiconductor (CMOS) integrated circuits. In contrast to previous modeling approaches, it does not require empirically constructed specialized analytical equations for the power macromodel, and obtained statistics of a circuit’s primary outputs simultaneously. It is suitable for power estimation in core-based systems-on-chips (SoCs) with pre-designed blocks. In experiments with the ISCAS-85 circuits, the average absolute relative error of the macromodel was below 5.0% for not only the average power dissipation, but also the maximum power dissipation.