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This paper presents a power-efficient 10-bit SAR ADC. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain under a low power supply voltage, thereby reducing noise and offset. Statistical estimation and loading switching techniques are synergically combined to further improve the energy efficiency. Moreover, the SAR sequencer and clock generator...
A configurable neuro-inspired inference processor is designed as an array of neurons each operating in an independent clock domain. The processor implements a recurrent network using efficient sparse convolutions with zero-patch skipping for feedforward operations, and sparse spike-driven reconstruction for feedback operations. A globally asynchronous locally synchronous structure enables scalable...
A 21mW low-power embedded Recurrent Neural Network (RNN) accelerator is proposed to realize the image captioning applications. The low-power RNN operation is achieved by 3 key features: 1) Quantization-table-based matrix multiplication with RNN weight quantization, 2) Dynamic quantization-table allocation scheme for balanced pipelined RNN operation, and 3) Zero-skipped RNN operation using quantization-table...
An energy-quality scalable (EQSCALE) feature extraction accelerator for IoT vision applications is presented. Knobs are introduced to dynamically adjust the tradeoff between energy and feature extraction quality, leveraging the intrinsic redundancy in video frames and the robustness of object recognition against missing features. Measurements of a testchip in 40nm show 310pJ/pixel energy at nominal...
Hand gesture recognition is one of the secure natural user interface (NUI) mechanisms on wearable devices since it does not reveal user's intention in public domain unlike the speech recognition. However, its energy dissipation is very demanding as it requires compute-intensive machine vision processing. Recently, wake-up detectors have been proposed to improve the energy-efficiency of always-on sensing...
This paper presents an 18-to-23 GHz sub-harmonically injection-locked all-digital PLL (SIL-ADPLL). It adopts the proposed injection-locked frequency divider aided adaptive injection timing alignment technique and uses a proposed (UP-DN) block to adjust the injection timing adaptively at output frequency higher than 20 GHz with low power consumption. A new pulse generator is proposed to relax the trade-off...
This paper presents a fractional-N sub-sampling phase-locked loop (SSPLL) for spread-spectrum clock generator. A digital-to-time converter (DTC) is adopted to facilitate a fractional-N SSPLL. A digital calibration scheme is employed to eliminate DTC gain error. With the calibration method enabled, the PLL is successfully locked and achieves 18.98-dB EMI reduction. This PLL was fabricated in a TSMC...
A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for an intra-panel interface is presented. Phase emphasis is introduced into the final 2:1 stage of a 20:1 serializer to reduce the data-dependent jitter without increasing IO capacitance, by making the transition timing depend on previous data. This is combined with LVDS channel drivers which control the common-mode voltage...
A dual-mode NRZ/PAM-4 differential low-swing voltage-mode transmitter employs a quarter-rate output multiplexing architecture for low-power operation. In NRZ mode, 2-tap feedforward equalization is realized with analog replica-bias tap control that is configurable in high-performance controlled-impedance or energy-efficient impedance-modulated settings. This analog control also allows for efficient...
This paper proposes a voltage reference operating up to 170 °C for low-power high-temperature systems. The proposed circuit buffers body voltages to avoid degradation of temperature coefficient from nwell/psub diode leakage. For low power overhead, it measures the diode leakage and adaptively adjusts the bias current of the buffers. This enables low power consumption at low temperature, which can...
In this paper we present the first fully integrated analog LDO (low dropout regulator) for sub-0.5V supply voltages. The LDO can operate from 0.3V-to-1.0V input voltage, and can sustain a load variation of 10mA-to-100mA at 1.0V input and 5mA-to-25mA at 0.3V input. It achieves a peak 99.1% current efficiency for a 100mA load at 0.9V output voltage. In order to realize the gate drive at sub-0.5V supply...
A proposed phase-interpolator (PI) based hybrid digital pulse width modulator (DPWM) effectively resolves the trade-off between resolution and power consumption. Conventional DPWM delay-line-based architectures suffer from high power consumption limited delay time per delay-tap due to process technology, while the proposed solution replaces the delay line with a PI featuring sub-gate-delay resolution...
A fully-integrated active matrix light-emitting diode (AMLED) micro display system is presented. The system consists of a 36×64 pixel-drivers encompassed by a fully on-chip hybrid voltage regulator built on the same silicon chip, then integrated with the AMLED array by using the flip-chip bonding technology. As such, no external passive component is needed. The hybrid voltage regulator consists of...
A dual strong-arm (DSA) comparator is designed targeting at low-voltage operation in deeply-scaled technologies. The addition of a second regenerative latch helps reduce both offset sensitivity and offset while maintaining comparable or better performance as a conventional double-tail latch across a wide range of voltages. A large comparator offset measurement array is fabricated in a 28nm FDSOI process...
This paper presents a power-efficient single-loop continuous-time (CT) third-order sigma delta (ΔΣ) modulator that achieves a SNDR of 79.6 dB over a 10 MHz signal bandwidth. The modulator uses a feedforward-feedback (CIFF-FB) architecture which incorporates a single amplifier biquad (SAB) and a passive integrator to realize a third-order noise shaping. We also propose a continuous-time complementary...
This paper presents a 2-2 discrete-time sturdy multi-stage noise-shaping (SMASH) delta-sigma modulator using source-follower-based open-loop integrators. The resolution of the SMASH delta-sigma modulator is enhanced by eliminating the first-stage quantization noise from the output. Using the proposed source-follower-based open-loop integrator, the operating speed of the modulator is efficiently improved...
This paper presents a compact audio delta-sigma modulator that features a scalable bandwidth to also support biomedical instrumentation such as digital hearing aids and electromyography, sustaining constant FoMS. The modulator achieves a small die area and low power consumption by exploiting the proposed dynamic gain-bandwidth-boosting (GBWB) scheme in the inverter-based class-AB OTA with minimal...
A scaling-friendly and PVT-robust pipelined SAR ADC reusing the first-stage comparator as a regenerative residue amplifier is proposed in this work. A low-power self-timed gain control block is combined with a mixed-signal background calibration to ensure a stable amplifier gain across PVT variation. A 130nm CMOS prototype achieves a peak Walden FoM of 9.2 fJ/conv-step and a Schreier FoM of 172 dB.
A fully-synthesizable Physically Unclonable Function (PUF) with hysteresis-enhanced stability and active compensation of temperature variations is proposed. In detail, a bitcell based on low-voltage regulated Cascode current mirror is introduced. To reduce undesired bit flips, hysteretic behavior is obtained through the insertion of a Muller C-element output stage, which mitigates the effect of noise,...
Dedicated hardware accelerators enable energy-efficient implementations of radio and imaging basebands. Multistandard, multi-mode radio basebands require an on-the-fly reconfigurable fast Fourier transform (FFT) accelerator that implements many different FFT sizes. An instance of a runtime-reconfigurable 2n3m5k FFT accelerator was generated by a custom hardware generator to meet the requirements of...
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