The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This work presents an area-efficient voltage and frequency scalable clock generator for low-power digital SoC clocking. Named Direct Digital Sampling and Synthesis (DDSS), the open-loop generator implemented in 28 nm FD-SOI operates from 0.45 V to 1.1V with measured jitter from 1.7% to 5.1% UI. Its low power consumption of 0.40pJ/cycle at 57 MHz 0.5 V combined with the ability to perform fast frequency...
This paper presents a multi-purpose built-in selftest circuit to reduce large design overhead in preparing various tests of high-speed links. The proposed circuit can be configured as a pattern generator, a pseudo-random bit sequence generator, a scrambler, a descrambler, or a snapshot, all of which are frequently used in various link tests but also require significant design effort. T o reduce the...
A 56Gbps PAM-4 optical receiver front-end is presented. In order to reduce the input-referred current noise of the receiver front-end, the shunt feedback resistor Rf of the TIA is enlarged. And, the equalizer is inserted to boost the high-frequency gain and extend the bandwidth. The AGC amplifier using the proposed dB-linear VGAs is further to lower the noise. This PAM-4 optical receiver front-end...
This paper presents a 1/4-rate PAM4 receiver employing a sampling decoder with an adaptive variable-gain rectifier (AVGR) to achieve a bit efficiency of 1.38 pJ/bit. By concurrently performing gain adaptation and amplitude rectification for decoding the least significant bit (LSB), the proposed decoder greatly reduces power consumption compared with the conventional full-rate topology using three...
This paper describes an energy-efficient PAM-4 digital receiver based on sequence detection. This scheme takes advantage of the ISI in the channel to reconstruct the time domain 5-bit sequence including MSB and LSB. The architecture also enables built-in error correction with very low latency. This concept is demonstrated with prototype implemented in a 28nm FDSOI CMOS using only 18-data comparators...
A quarter-rate 51Gb/s PAM4 CDR with decoded dual-NRZ outputs is presented for 400GbE optical transceivers. A baud-rate data-only sampling PD with zero-crossing integrating front-end is proposed to minimize the clock generation and distribution overhead, as well as improving the noise resilience under PAM4 low-SNR inputs. Measurement results show the CDR features 1.08ps RMS clock jitter, 3.4×10−9 PAM4...
This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running...
This work presents a fundamental-mode voltage-controlled oscillator (VCO) realized in a 130 nm SiGe BiCMOS process for operation up to 200 GHz. The implemented topology is derived from a feedback phase shifter design, which includes a wideband passive polyphase filter based on 90° and 180° transmission line couplers and a variable-gain active combiner. The fabricated circuit achieves a very large...
An ultra low phase noise millimeter-wave (mm-wave) quadrature voltage-controlled oscillator (QVCO) is proposed. By introducing an additional coupling path and using uneven sized cross-coupled oscillators with a fully symmetrical layout, the phase noise and the amplitude/phase mismatches are minimized. Implemented in 90-nm CMOS process, the 67-GHz compact QVCO achieves 0.46 degree and 0.47 dB phase...
We propose a ring-based quadrature LC-tank oscillator for Internet-of-Things (IoT) that can operate under a 350-mV supply voltage of energy harvesters. The oscillator is based on a series LC tank, with additional control circuitry to realize a nearly instantaneous start-up of one/two RF cycles to facilitate a deeply duty-cycled burst-mode operation of IoT. Fabricated in TSMC 28nm CMOS, the prototype...
Two techniques for spur and phase noise cancellation have been proposed. A fully integrated design achieves a measured spur cancellation of 15dB at 250MHz and 750MHz offset as well as phase noise cancellation from 4MHz to 200MHz offset with maximum 25dB cancellation depth for a 1-GHz clock. The proposed ideas have been verified through a fabricated 65nm CMOS prototype with power consumption of 11mW...
In this paper, a single-inductor triple-input-triple-output (SITITO) buck-boost converter with cycle-by-cycle source tracking (CCST) is developed for multi-source energy harvesting. The proposed CCST is capable of harvesting power from the PV and TEG simultaneously, and automatically selects the appropriate source according to the maximum power point (MPP) of the transducers in each switching cycle...
This paper presents a novel three-dimensional maximum power point tracking (3D-MPPT) system for ultra-low power (ULP) solar energy harvesting systems (EHS) for internet of things (IoT) smart nodes. The proposed 3D-MPPT utilizes a gate-source voltage (Vgs) dependent switch width modulation (SWM) technique for improving power efficiency (PE) at standby (<1 μA) and heavy (>300μA) load scenarios,...
The proposed dynamic voltage scaling (DVS) based burst mode links the DVS technique in a system on a chip (SoC) and the burst mode operation of the DC-DC converter for further efficiency improving. Conventional burst mode has only one entrance transition point (ETP) between the pulse width modulation (PWM) and the burst mode, so the voltage ripple is high at low DVS voltage while the efficiency is...
A new switched capacitor (SC) converter for powering miniature sensor systems with wide load current and output voltage ranges is proposed in this paper. By adopting a multiple-ratio SC stage and reconfigurable stage interconnect scheme, the proposed converter offers fine granularity of conversion ratios, which improves efficiency for light load operation. The multiple-leaf structure for switch size...
State-of-the-art closed-loop switched-capacitor (SC) designs usually regulate the output voltage by pulse frequency modulation (PFM) with the disadvantage of large electromagnetic interference (EMI). It may cause the failure of the Internet of Everything (IoE) devices. This paper proposes the hybrid digital low drop-out (DLDO) SC converter with a constant switching pulse width modulation (PWM) control...
This paper presents a CMOS time-of-flight (TOF) image sensor with in-pixel background light cancellation for outdoor depth imaging application. The using of P+/N_well diode with proposed polarity switching integration and phase-shift readout (PSR) technique achieves the in-pixel background cancellation capability and sensitivity improvement. Moreover, the PSR also suppresses the column fixed-pattern-noise...
This work presents a compact ADC architecture capable of digitizing the signals received by every individual element of a 2D ultrasound transducer array. An element-matched layout of 150 μm × 150 μm is realized by exploiting each piezo-electric transducer element not only as the signal source, but also as the electro-mechanical loop-filter of a continuoustime band-pass ΔΣ ADC, thus minimizing the...
A power-efficient analog beamforming embedded SAR ADC for ultrasound imaging systems is presented. It is constructed from multiple sub-beamforming SAR ADCs, which sequentially perform analog beamforming and analog-to-digital conversion for an assigned focal point on a scan-line. Power is saved because these operations are carried out in the charge domain without a summing op-amp. This is realized...
A low-power and high-accuracy current driver IC is proposed for portable electrical impedance tomography (EIT) systems. The proposed IC supports active electrode configuration and has three key features. First, high output impedance current driver is implemented with phase compensation scheme through a delay-locked loop (DLL) to significantly alleviate a phase shift and a required power consumption...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.