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We propose a built-in test circuit to detect resistive open defects occurring at interconnects between dies of 3D ICs. The test circuit consists of an I-V converter and a comparator of offset cancellation type. Feasibility of the tests with the circuit is examined by SPICE simulation. It is shown that resistive open defects of 5Ω and above can be detected per 240nsec under process variations of MOSs...
We have proposed a power supply circuit and an electrical interconnect test method based on charge volume supplied from the power supply circuit. We optimize the supply circuit so as for small resistive open defects that occur at interconnects among dies in 3D stacked ICs to be detected by the test method. We examine what resistive open defects can be detected with the optimized power supply circuit...
In our previous study, we argued that stabilization of power source voltage by optimizing a chip wiring feature was essential to achieving high performance transmission for over 40 Gbps I/O on an interface circuit. This region frequency transmission approach is fairly important to solve communication bottleneck. We will examine power supply wiring for more high frequency (over 40 Gbps) which is significant...
This paper proposes an equivalent model of the coupling capacitance between TSVs and adjacent RDL. Based on the scalar potential integral equation and cylindrical accumulation mode basis functions, an efficient method of extracting the coupling capacitance is present. The scalability of the proposed model is verified by simulation and our results show that an accuracy of 10% is achieved from the analytic...
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