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Conventional Extended gate STI based LDMOS devices often have an overlap between gate and STI resulting in higher impact ionization at the STI left edge. In this work, we have proposed and analyzed a novel split gate architecture to reduce impact ionization and improve off-state breakdown voltage. The underlying physics behind the improved characteristics of the proposed architecture is explained...
In this study, the impact of Metal-Interlayer-Semiconductor Source/Drain (MIS S/D) structure on enhancement mode 7nm n-type germanium (Ge) junctionless FET (JLFET) is demonstrated with Sentaurus 3-D technology computer-aided design (TCAD). The device using MS S/D structure cannot operate for normally-off mode because of severe Fermi-level pinning (FLP) and using MIS S/D structure can be a solution...
This paper presents an analog baseband chain for automotive radar applications. The baseband chain consists of a fifth-order Butterworth filter with a reconfigurable bandwidth and a 3-stages programmable gain amplifier (PGA) with DC offset cancellation (DCOC). To achieve robust temperature stability, an amplifier with resistive feedback topology is employed, while temperature compensation technique...
In this paper, we present a low-voltage receiver capable of operating from 0.5–3GHz. The single-stage receiver is designed in TSMC 65nm technology, and is capable of operating at supply voltages of 0.6–1.2V. It is matched to a differential impedance of 100Ω, with an input reflection coefficient that is better than −10dB over the desired frequency range. A gm-boosting loop based on a class-AB transconductor...
A U-band oscillator is presented as a divide-by-two direct injection-locked frequency divider (ILFD), with NMOS injection transistors coupled to the LC oscillator. Compared with the both NMOS and PMOS injection transistors, the NMOS only injection transistors contribute to a much wider locking range. The strategy to choose the structure and sizes of the injection transistors for symmetry and the locking...
Epitaxial tunnel layer tunnel FET (ETL TFET) is one of the promising device for ultra-low power applications. In this work, device performance between planar ETL TFET and Fin ETL TFET are evaluated. For n-type TFET, the electric field enhancement in Si region due to the fin structure results in Si-to-Ge and Si-to-Si tunneling at low voltage so that the subthreshold swing is degraded. For the p-type...
The Keyed-Hash Message Authentication Codes(HMAC) is a useful mechanism for message authentication. In this paper, a high-performance HMAC/SHA-3 processor which can generate HMAC message digest and hash message digest is presented. Not only the standard length (224,256,384,512) of the message digest can be generated, but also a length of 64-bit message digest. Due to the application of new generation...
Airborne ultrawideband radars operating at VHF/UHF frequencies can be used to sound and image polar ice sheets with fine-resolution. The sensitivity of the radar depends upon the power-aperture product. High peak power coupled with a large aperture is required to sound more than 4-km thick ice. In this paper, we present the design of a 400-W power amplifier for operation over the frequency range of...
This paper presents the effect of side diffusion and doping concentration profile produced by two different ion implantation model for UHV LDMOS device with Linear P-top and its effect on device performance. The result shows that the device using Monte Carlo Model have different side diffusion with different N-Epi layer background whereas Taurus Table is unable to explain the side diffusion and Monte...
For power semiconductor devices, such as IGBTs, MOSFETs and FRDs, a high area efficiency of the edge termination structure can enlarge the active area and thus improve the current capacity for a given chip area. In this paper, a double-sided edge termination (DSET) is proposed for the first time. Simulation results show that it can improve the breakdown voltage by about 42% without increasing the...
A 10 GHz 4-phase ring-VCO based injection-locked clock multiplier (RILCM) for 40 Gb/s SerDes application is presented in this paper. The RILCM adopts two loops which share common part circuit to realize the injection lock. The first loop which is the frequency lock loop (FLL), drags the VCO's free-running frequency to the injection lock-in range. Another loop which is the injection timing control...
A continuous-time Delta-Sigma modulator (CTDSM) using passive low pass-filter (LPF) in the feedback DAC is proposed. The LPF helps to reduce the signal swing and slew-rate requirements of the first amplifier in CTDSM and also contributes one-order noise shaping. A modulator synthesis is analyzed. The performance of the modulator has been verified through simulations using a standard 0.18-μm CMOS process...
This paper presents a novel subthreshold Darlington pair based negative bias temperature instability (NBTI) monitoring sensor under the stress conditions. The Darlington pair used in the circuit provides the stability of the circuit and the high input impedance of the circuit makes it less affected by the PVT variations. The proposed sensor provides the high degree of linearity and sensitivity under...
High temperature modelling of GaN HEMTs requires a knowledge of the temperature dependency of low field channel mobility and parasitic source / drain resistances. We discuss extraction of this dependency from drain current versus gate voltage curve at small drain-source voltage.
Many semiconductor industries gradually tend to transit from the complex 2D design to a high regularity of 1D gridded design. In this transition process, cut distribution position has become the most important challenge. For more advanced nanometer designs, cuts may be too dense to be printed by 193i lithography. While Directed Self-Assembly (DSA) is outstanding in recent years, it is a great potential...
This paper presents a Flash ADC with low offset dynamic comparators using an offset cancellation technique. By dynamically storing the comparator offset on the input capacitors, the offset is suppressed mostly. Two 5-bit 160MS/s Flash ADCs (Flash-A using the proposed offset cancellation technique and Flash-B without cancellation) are fabricated in 65nm CMOS for comparison. The measure results show...
This paper presents a 2-input and 3-output 0.35–1.5GHz switch cell with active balun. The proposed differential switch cell is composed of 8 differential series-shunt-series switches which improve the transmit efficiency of switch cell. Two wideband active baluns are used to compensate for the loss of passive switch cell which almost consumes no DC power. Fabricated by 0.18μm SiGe BiCMOS technology,...
Since large array devices of MOSFETs are huge for driving capabilities, ESD self protections are also required. Then, the large drain-contact-to-poly-gate-spacing layout rule is usually adopted with large layout areas. In this paper, a new control circuit is implemented for adopting the minimum device layout rule in the LAD. Hence, it results in a very small layout area and ESD self-protection capabilities...
The electrical and optical characteristics of the three port InGaN/GaN blue quantum-well heterojunction bipolar light-emitting transistors (QW HBLETs) on sapphire substrate are reported. The base-emitter (BE) light-emitting diode and base-collector (BC) diode are demonstrated. Next, the Gummel-poon plot is measured. Moreover, the collector current-voltage (I-V) and light-current-voltage (LI-V) characteristics...
This paper presents a clock-feedthrough compensation technique for bootstrapped switches. The proposed technique utilizes a dummy transistor to generate a reverse voltage, which compensates the input-dependent error caused by clock feedthrough effect of sampling switch. Simulation result shows the differential sampling error of bootstrapped switch reduces from 7.2mV to 1.4mV for the worst case, operating...
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