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Elliptic curve cryptography(ECC) has gained tremendous popularity and the selection of coordinate systems has a significant impact on basic point doubling and point addition operations. In this paper, we investigate into the best suited coordinate systems corresponding to scalar multiplication with a fixed point as well as with an unfixed point and give out implementation schemes in both cases. Besides,...
Large number addition is the fundamental operation in cryptography algorithms. In this paper, we accelerate large addition in hardware design by introducing non-least-positive form, which is beneficial to parallel processing. An implementation of 256-bit signed array accumulator with our method shows an improvement of 18% in speed and 15% in area-delay product compared with traditional design.
MoO3−x-based Transition Metal Oxide Resistive Random Access Memory (ReRAM) devices were fabricated using atomic layer deposition, and their resistance-switching behaviors were investigated. The bipolar phenomenon was observed when 100-nm-thick Au were deposited by electron beam evaporation as bottom electrode (BE) and top electrode (TE), respectively. The proper electrical properties, such as excellent...
In this letter, a diode trigger silicon-controlled rectifier (DTSCR) with small diode width is proposed for Electrostatic discharge (ESD) protection of the low-voltage integrated circuits. The trigger voltage of DTSCR is adjusted by the width of the diodes which are used to trigger on the SCR device. Experimental data show the trigger voltage increases with decreasing the area of the diodes. The trigger...
An op-ampless second-order compensated bandgap reference with low temperature coefficient is proposed in this paper. The bandgap is second-order curvature-compensated by the temperature coefficient of the threshold voltage of a MOSFET. Simulated by Spectre, the output reference voltage is 1.102V with a 2.7ppm temperature coefficient from −40 °C to 160 °C and a −60dB PSRR at low frequency. The current...
This paper presents a design of command queuing engine in eMMC5.1 host system. With the proposed engine, multiple commands can be collected and executed in order of priority instead of executed as they arrive. The proposed engine helps reducing latency on small data transfers so that performance in multitasking scenarios is improved. This design is verified by simulation for various requests and the...
A novel PWM/PFM hybrid-mode auto-change technique for buck DC-DC converter is proposed. The proposed technique utilizes the comparator propagation delay to decide the mode changing point without adding complicated PMW/PFM hybrid-mode controller. The proposed concept enables compact and simple implementation of hybrid-mode buck DC-DC converter. Simulation results show that the buck DC-DC converter...
A five-stage 93.9 GHz-105.6 GHz common-source CMOS amplifier is presented in this paper. The customized on-chip inductor and transmission line (TL) are designed for matching networks. Fabricated in a 65nm bulk CMOS process, this amplifier achieves a peak gain of 9 dB at 100 GHz and 11.7GHz 3-dB bandwidth range from 93.9 GHz to 105.6 GHz, consuming total power of 49.2 mW under 1.2 V voltage supply...
Visible light communication (VLC) has recently become one of the most popular research points. VLC can provide not only illumination, but also the data communication. This technique can be applied in the indoor localization system when it transmits information of location. Global Positioning System is usually unavailable in the building. Indoor localization using VLC is a solution to solve this problem...
In this paper, we implement the Wi-Fi hardware architecture. The core chip designed by the MediaTek Corporation is used to develop its peripheral circuits. The chip supports USB Type and can control the lighting circuit through the APP on the mobile phone, so as to simulate the switch of household electrical appliances. In the future, consumers can purchase home appliances with built-in communication...
Two hybrid memristor-MOS exclusive OR (XOR) and exclusive NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed gates present logic states with voltages, and implement the logic operation within one clock cycle. The designs ease the voltage degradation problem of the original MRL logic gates, while consuming fewer area overhead and less delay than their counterparts.
Through-silicon vias (TSVs) is one of the key enabling technologies of 3-D ICs. However, the crosstalk problem among the adjacent TSVs decreases the performance and deteriorates the signal integrity of TSV bus. This paper proposes an exhaustive search technique of 6C crosstalk avoidance codewords that is applicable for TSV arrays of different sizes to suppress the crosstalk noise below 6C level. The...
In this paper, a new PNPN tunnel field-effect transistor with L-shaped gate (LG-PNPN TFET) is proposed and investigated by numerical device simulator bringing significant on-state current enhancement. Higher drive current is achieved at VDD = 1.0V than traditional PNPN TFET because of both the line and point tunneling between the source and N+ pocket. Key parameters like the pocket width and doping...
This article proposed chip antenna and low noise amplifier with band pass filter for wearable and biomedical design has been successfully implemented. This integrated analog chipset has setup near-infrared laser-driven (NIRLD) might be a promising wireless electrical power source and phase in wake up receiver technology using direct active RF detection for biomedical nano-devices power saving.
A full-load low-dropout regulator (LDO) based on proposed hybrid compensation structure is proposed. The proposed LDO makes use of an NMOSFET power transistor. The LDO is able to be stabilized for 0 to 1-μF capacitive load. Experimental results prove the LDO stability and fast recovery speed.
In this paper, we have explored the impact of different gate architectures in controlling short channel effects in scaled AlGaN/GaN HEMT devices using calibrated 2-D TCAD simulations. Devices with different gate topologies, namely I-Gate and T-Gate are investigated for their efficacy in minimizing the short channel effects. Various parameters like transconductance, channel conductance and drain induced...
The design of a four-stage common-source (CS) 150 GHz amplifier in a 65nm technology is described. Each stage bases on the proposed technique of coupled transmission line (T-line) neutralization to achieve an improved intrinsic gain. Coupled T-line is also used for impedance matching, including both input and output, and inter stage impedance matching. Simulations show that the proposed amplifier...
The application of shallow trench isolation (STI) as trench capacitor is proposed in CMOS image sensor (CIS) to provide variable conversion gain. This provides higher sensitivity without degrading the dynamic range (DR) of the pixel. The proposed structure uses in-built isolation trenches as capacitors. In case of low light, trench capacitor (TC) is disconnected from the floating diffusion (FD) node...
We present a type of high performance contact-separation mode triboelectric generators (TEG). The TEGs consist of a poly(vinylidene fluoride) composite with embedded barium titanate nanomaterial (PVDF-BaTiO3) and polyamide-6 (PA6). Additional BaTiO3 nanomaterial in the PVDF increase the relative permittivity and piezoelectric effect, thus enhance the performance of the TEGs. Owing to the increased...
This paper presents a simulation study to achieve wide-linear-range transconductance of T-gate GaN HEMTs by introducing a δ-doped layer and a p-GaN back barrier. With optimized δ-doping density and location, the transconductance (gm) and current gain cutoff frequencies (fT) are ultra-flat and remain close to their peak values over a wide range of gate-source voltages (Vgs). In addition, a smaller...
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