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A high-throughput architecture of the CCSDS 122.0-B-1 image compression standard is proposed. The architecture uses a novel memory organization in order to reduce the total memory operations and the number of the individual memories allowing operation without external memories. The architecture has been implemented on space grade and commercial FPGA Device. It achieves 136 MSamples/sec on space grade...
In 3D integrated circuit (3D-IC), there are two or more layers of active electronic components which are integrated both vertically and horizontally. Through-silicon-via (TSV) is used as the vertical electrical connection which enables a great deal of functionality packed into a small footprint. In this work we solve the signal TSV assignment problem in 3D-IC taking thermal problem into consideration,...
Heterogeneous multicores provide alternative core types and potentially multiple voltage-frequency levels to execute workloads more efficiently. One fundamental obstacle for capitalizing their potential performance and energy gains is identifying the most appropriate configuration (core type and voltage-frequency pair) for executing the computations at hand. In this paper, we analyze an ARM big.LITTLE...
Sub-threshold circuit is a promising circuit design style for IoT application, but the timing closure, especially hold timing fixing is a big challenge for designers. This paper proposes a mathematical method to estimate the number of insertion inverters/buffers for hold timing fixing in each short path. Firstly, the distribution of path delay is rigorously proved to be lognormal distribution in the...
Achieving a power envelope of few milliwatts combined with tight performance constraints is emerging as one of the key challenges for battery-powered and low cost Internet-of-things (IoT) end-nodes. IoT devices have to cope with highly time-varying workloads, characterized by intermittent “race-to-sleep” bursts of compute-intensive operations mingled with long periods of low activity. Architectural...
Computing circuits suffer from the process, voltage and temperature variations and aging. These factors reduce yield and lifetime of the circuits and therefore limit the advance in modern computing technology. The process variations and aging result in timing failures that often can be resolved by delay matching. However, this strategy requires delay elements which cause additional power cost. We...
Power modelling is important for modern CPUs to inform power management approaches and allow design space exploration. Power simulators, combined with a full-system architectural simulator such as gem5, enable power-performance trade-offs to be investigated early in the design of a system with different configurations (e.g number of cores, cache size, etc.). However, the accuracy of existing power...
In this paper, we present extensions to the floating point unit of the RISC-V ISA with different numeric precision including single precision, half precision and quarter precision. To achieve more energy efficiency transprecision feature is introduced through configurable mantissa precision, which can be used to reduce the number of iterations and thus reduce the energy consumption achieving a programmable...
Internet services tend to include more and more multimedia traffic. Exchange of high resolution video and voice streams is now many users' common need. To cope with the increasing requirements of video transmissions in sufficient time and optimal bandwidth without quality loss, effective compression algorithms are required. The Quadtree Structured Differential Pulse Code Modulation (QSDPCM) technique...
In this paper, we propose Without Charge Sharing Quasi Adiabatic Logic (WCS-QuAL) as a countermeasure against Power Analysis Attacks. We evaluate and compare our logic with the recently proposed secure adiabatic logic designs SPGAL and EE-SPFAL at frequencies ranging from 1MHz to 100MHz. Simulation results show that WCS-QuAL outperforms the existing secure adiabatic logic designs on the basis of %...
This paper presents the design, simulation implementation and evaluation of a novel 3D NoC router that combines buffered and bufferless routing. Our proposal is an asymmetrical router that is buffered in the z dimension and bufferless in the x- and y dimensions. Experimental results show that the proposed router effectively combines the advantages of both buffered and bufferless routers. Compared...
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