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The research used TRIZ innovation methodology which included the model of the technical contradictions, physical contradictions, and the inventive theory of asymmetry — preliminary action · nesting — extraction principles, to optimize the design and improve the Lamp anneal process of diffusion machine. The inventive embodiment consisted of the following four parts as: 1. Add the wafer Pre-clean step,...
In a semiconductor manufacturing processes such as Wafer Level Chip Scale Package, yield is one of the Key Performance Indicator. Yield is also an indicator for Quality, Productivity and OEE. If the yield is below the limits or cut-off, it said to be that there is a sign of poor quality since the process is rejecting Wafer or Dice affected by different defects either by Electrical or by Visual Mechanical...
Plasma induced damage (PID) during high density plasma (HDP) chemical vapor deposition (CVD) deposition is a challenge for fabricating metal oxide semiconductor field effect transistors (MOSFETs). In this paper, reducing the plasma-induced damage to the thin gate oxides during inter-metal dielectric (IMD) gap-fill process is investigated. Applying in-situ silicon-rich oxide (SRO) or silicon oxy-nitride...
This paper discussed real-time solutions to product-mix scheduling problems (PMSPs) when a loading or a capacity of Fab are dynamically changing. The objective is that maximization of the resource utilization while keeping a due date and Q-time restrictions of every production lot. Particularly, two methods, P3D (Pseudo-Periodically Priority Dispatching) and the Palmer, are introduced for Make-to-Stock...
Japan Semiconductor Corporation (JSC) has been mainly manufacturing 8inch product wafers at 2 facilities, located at Iwate and Oita in Japan (Figure1). At present, both operations are sharing 80% or more of the processes(Figure2). Furthermore, we are advancing the improvement of both facility and production equipment in order to achieve “PGA 500Gal”. ∗PGA : peak ground acceleration.
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