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Content addressable memory (CAM) performs parallel data search at the cost of high area and power penalty. We propose a high-speed 6T-ReCSAM (Reconfigurable CAM/SRAM) with new energy efficient sensing technique. Proposed implementation is compatible with compact 6T-SRAM foundry bitcells. Test-macro of 8Kb is implemented in 28nm FDSOI CMOS and reaches up to 1.56GHz at 0.9V with 0.13fJ/bit energy consumption...
The demand for more and more efficient management of power systems is causing BCD technologies to move forward in the integration of additional digital functions, and the use of microcontrollers in products has become a common practice. In this perspective, the introduction of an embedded nonvolatile memory (eNVM) to store the microcontroller code has become important to enable software customization...
This paper presents a 2×14bit cartesian Direct Digital RF Modulator (DDRM) in 28nm CMOS. Both AM and PM calibration circuits are introduced to relax matching requirements of the DDRM units which results in a compact and efficient implementation. The DDRM features a memoryless current source based unit cell to avoid complex dynamic digital predistortion (DPD) algorithms. All the units can be tuned...
This paper presents a low voltage 5GHz WLAN receiver (RX) with 0.8V power supply. The RX targets 802.11ax standard implemented in CMOS technology node from 28nm to 14nm whose power supply voltage will decrease to 0.8V. The RX presents three key techniques that overcome the challenges for the low voltage operation. An RF amplifier employs a variable source degeneration to improve the linearity. A quadrature...
This paper describes a fully integrated 65nm CMOS 2×2 MIMO multi-band LTE RF transceiver for small cell (femtocell) base stations with frequency support from 680MHz to 6GHz. The transceiver features highly integrated RF front-ends including single-ended LNAs and drive amplifiers with total 32 individual RF I/O pins. The receiver shows NF of 2.9∼5.2dB, HP3 of >-2dBm, and HP2 of >48dBm over the...
A low-power radio analog front-end which includes a self-interference (SI) cancellation circuit and a harmonic-rejection power amplifier (HRPA), is proposed to reduce the interaction between a transmitter (TX) and receiver (RX), to enable full-duplex operation. A prototype TSMC device demonstrates more than 30dB SI cancellation over a 4MHz BW and a PA 3rd and 5th harmonic reduction of 30dB and 15dB,...
The latest extended-coverage (EC-GSM-IoT) and high-throughput (EGPRS2A) enhancements make GSM competitive to LTE-based cIoT standards such as NB-IoT with the advantage of global coverage today. This work introduces the first fully-integrated RF-SoC supporting the complete GSM standard family ranging from EC-GSM-IoT through EGPRS2A. The RF-SoC achieves −121.7 dBm receiver sensitivity and peak data...
This paper presents a LED driver IC based on a self-resonant Hybrid-Switched Capacitor Converter (H-SCC) operating in the MHz range. Capacitors and switches of the LED driver are integrated on-chip in a low-cost 5V 0.18μm bulk CMOS technology. The effective chip area is 7.5mm2. A conventional SMD output capacitor and a 6.4 mm2 150nH SMD air-core inductor are enough to operate the driver in a compact...
The presented wide-Vin step-down converter introduces a parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300 nH resonant coil, placed in parallel to a conventional buck converter. Unlike conventional resonant concepts, the implemented soft-switching control eliminates input voltage dependent losses over a wide operating range. This ensures high efficiency across...
The stacking MOSFET structure composed of low-voltage devices suffers from deteriorated transient response or large footprint area when capacitor-free or dominant pole compensation low dropout (LDO) regulator biases the driver. Due to self-stabilized feature, the proposed stacking MOSFET driving (SMD) technique effectively drives the power stage and greatly reduces noise interference from the noisy...
This paper presents a sub-pA current read-out interface that consists of a series connection of a low-noise current amplifier and a second-order continuous-time Delta-Sigma modulator. Contrary to the approach to the current amplification by means of a series connection of a charge integrator and differentiator, no reset and thus no interruption of the current-to-digital conversion needs to be performed...
We present here a single-chip platform for Hall-based magnetic sensing. When configured as an angle sensor, the achieved accuracy of 0.5 ° improves the state of the art of Hall-based integrated angle sensors targeting automotive applications (with extended temperature range up to 160 °C. This is achieved thanks to a low offset front-end (< 15 μV) and individual trimming of the Hall element sensitivities...
This paper presents a battery-connected wireless ion sensing system comprising a Na+-selective electrode, a 406 pW Potentiometrie front end, a 780 pW reference-free asynchronous SAR ADC, a 2.4 GHz power oscillator-based transmitter that consumes 2.4 nW when transmitting 100 bps, a 485 pW quiescent power 1.8-to-0.6 V switched-capacitor DC-DC converter with 96.8% peak efficiency, and two temperature-stabilized...
This paper describes the design of a high-density 4,096-pixel electrochemical biosensor array in 180nm CMOS for biomedical applications that require multiple analyte detection from small (5μL) samples. Each pixel of the array contains an exposed 45×45μm2 interdigitated micro-electrode surrounded by a ∼9pL nanowell fabricated using only a standard CMOS process along with a simple electroless gold plating...
An efficient near-field RFID reader, delivering power to and receiving data from Brain-Machine Interface implants, is realized in 65 nm CMOS. A modified Class E/Fodd Power Amplifier with a current-sense resistor differentially drives a single segmented antenna, and acts simultaneously as TX and RX. It operates at 309 MHz and has 54% efficiency. The backscattered data is recovered from the current-sense...
This work presents a fully-integrated sub-GHz radio System on Chip (SoC) for Low-Power Wide-Area Networks (LPWAN) and Internet of Things (IoT) applications. The receiver (RX) achieves 77dB blocker rejection and −106dBm sensitivity at 50kbps. The transmitter (TX) features a Switched-Capacitor Power Amplifier (SCPA) that delivers 13.5dBm output power. To fulfil stringent Japanese emission regulation,...
To enhance the mask rejection below 2 MHz for effective human body communication (HBC), a new mask shaping technique is proposed for the HBC transmitter, where a digital sigma-delta modulated infinite impulse response (IIR) filter provides sufficient rejection with a digital-to-analog converter (DAC) of only 8 bits. A receiver with high input impedance is designed to improve the sensitivity, and a...
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