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A 10-bit 1MS/s SAR ADC in 65nm CMOS is presented that introduces an Energy-Reduced-Sampling (ERS) technique to reduce the input drive energy for Nyquist rate ADCs. Our ADC occupies an area of 0.048 mm2, and achieves an SFDR of 67 dB, an SNDR of 56 dB at up-to 1MS/s and 3.2μW power consumption, yielding a Walden Figure of Merit, FoMw of 5.9fJ/conversion-step. Using ERS, the peak sampling current and...
This paper presents a calibration technique based on missing-code-detection (MCD) scheme to correct the gain error between the MSB and the LSB array in SAR ADCs with bridge-DAC structure. The MCD algorithm replaces the gain factor calculation with simple missing-codes count that significantly reduces the calibration digital overhead. It also relieves the linearity requirement of the testing signal;...
The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between −28.8 and −26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up to 6.4 Gb/s. Its architecture, based on subharmonic injection locking, is immune to pulling by the power amplifier. A 24 GHz phase-locked...
A 491.52 MHz CMOS crystal oscillator targeting 5G mobile systems and mmW frequency operation is presented. The high oscillation frequency is imperative to obtain low phase noise in mmW frequency synthesis. The oscillator operates in linear mode controlled by an amplitude feedback loop. Further, a FoM peaking at 256.6 dB with record low EVM contribution for a 5G OFDM signal is achieved, when compared...
A system for mmW LO signal generation targeting 5G is presented. The proposed concept achieves high LO spectral purity at mmW frequencies using standard CMOS SOI technology. The measured performance is in line with 5G outdoor system requirements, which due to multi-path propagation require a smaller sub-carrier spacing than recent indoor mmW systems like IEEE 802.11ad. A set of two fractional-N, PLL...
A new face detection SoC integrating CIS array with low-power face detector on a single chip in analog-digital mixed-mode is proposed for ultra-low-power mobile device applications such as always-on user authentication. The proposed event-driven mixed-mode face detection SoC performs Viola-Jones face detection with not only analog face detection circuits but also digital vision processor. The analog...
A deep learning processor with 8 gated recurrent neural network (RNN) accelerators is proposed in this paper. It features on-chip incremental learning by numerical and local gradient computation enhancement. Extra precision of training is obtained without extending the bit-width. Tri-mode weight access (DMA/FIFO/RAM) improves the throughput during incremental learning. The number multipliers and activation...
This paper presents IC realization of a random forest (RF) machine learning classifier. Algorithm-architecture-circuit is co-optimized to minimize the energy-delay product (EDP). Deterministic subsampling (DSS) and balanced decision trees result in reduced interconnect complexity and avoid irregular memory accesses. Low-swing analog in-memory computations embedded in a standard 6T SRAM enable massively...
Future implantable devices demand ultra-low power consumption with self-calibration capability providing real-time processing of biomedical signals. This paper introduces an adaptive processing framework for highly accurate on-chip spike sorting processing by learning the signal model in the recorded neural data. The novel adaptive spike sorting processor employs dual thresholding detection, adaptive...
A fully synthesizable analog-like loop filter for a Low-Dropout regulator using only digital standard cells is proposed. To accommodate this, various blocks such as comparator, time-to-digital converter and charge-pumps are developed using only standard cells. The fabricated prototype in 0.13μm process occupying 0.0875mm2 provides 15mA current with minimum quiescent current of 140μA and load transient...
A digitally controlled LDO in 14nm tri-gate CMOS powering an Atom™ core with embedded power gates enables per-core DVFS over a wide voltage-frequency range. The LDO demonstrates 99.6% peak current efficiency at 2.5A load current and provides a power density of 26.1 W/mm2. The multi-mode digital controller featuring non-linear mode and adaptive gain achieves <20ns settling time with a 100mV droop...
The paper proposes a power supply unit to efficiently supply always-on or duty-cycled IoT loads which consumes in μW-range. This PS achieves the highest 93% and 99% current efficiencies at average output currents of 1μA and 100μA to date, respectively. This unit includes a voltage reference and oscillator to generate autonomously duty-cycled power delivery operation as low as a 30μ8 on-period. The...
A switched capacitor dc-dc converter with frequency-planned control is presented. By splitting the output stage switches in eight segments the output voltage can be regulated with a combination of switching frequency and switch conductance. This allows for switching at predetermined frequencies, 31.25 kHz, 250 kHz, 500 kHz, and 1 MHz, while maintaining regulation of the output voltage. The controller...
Different from conventional multiphase switched-capacitor (SC) DC-DC converters, the proposed unsymmetrical parallel switched-capacitor (UP-SC) regulator provides more controllable input variables to increase available conversion ratios for improved load regulation. Even under higher conversion ratio numbers, the UP-SC regulator uses the fast searching optimum ratio (FSOR) technique to search the...
This paper presents a fully integrated dc-dc converter with on-chip double galvanic isolation. The converter exploits only two dice both fabricated in a 0.35-μm BCD technology with a thick-oxide back-end for 5-kV galvanic isolation. It uses a novel architecture to transmit power across two isolation barriers, which are performed by integrated capacitors and transformers. LC coupling inherently enables...
An energy harvester with a low startup voltage and wide input range is proposed mainly for solar power. In this work, neither any post-fabrication steps nor excessive external assistant components are required to startup the circuit with a low input voltage. Moreover, a voltage detector is proposed for widening the input voltage range. The proposed chip was fabricated by TSMC 0.18μm 1P6M mixed-signal...
A 900 MHz RF energy harvesting system is proposed for a far-field wireless power transfer application. The topology of a single-stage CMOS rectifier loaded with an integrated boost DC-DC converter is implemented in a 40 nm CMOS technology. The co-design of a cross-coupled CMOS rectifier and an impedance matching network is described to optimize RF-DC conversion efficiency for the target input power...
The POWER9™ Processor in 14 nm SOI FinFET technology makes use of 7 different families of arrays. This paper gives an overview on advantages of different implementations, focusing on two key innovations introduced with this processor generation: Fast and low-latency write assist schemes for single-voltage performance arrays, as well as a new methodology, the synthesized soft arrays, to enable significant...
Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional SRAM, due to its high-density, low-leakage, and inherent 2-ported operation, yet, its dynamic nature leads to limited retention time that requires periodic, power-hungry refresh cycles. This drawback is further aggravated in scaled technologies, where increased leakage currents and decreased in-cell storage capacitances...
In this paper, we propose an ultra-low-voltage (ULV) SRAM in 28nm FDSOI based on a 7-T ULP bitcell that allows using only low Vt (LVT) transistors for density and speed without prohibitive leakage. The retention is based on two CMOS negative-differential resistance (NDR) structures. Thanks to importance sampling (IS) methodology, the proposed bitcell has been sized to reach low failure rate for 8-kB...
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