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This work presents a novel Si-on-SiC laterally-diffused (LD) MOSFET structure intended to provide high breakdown voltage of 600 V and be resistant for harsh-environment space applications. Single-event effects (SEE) and total ionizing dose (TID) are investigated for the first time in such device. Initially, the considered Si LDMOS structure on SiC suffers from single-event burnout (SEB) at a drain...
We present a 5nm logic technology scaling step-up holistic approach for 5-track standard cell design employing electrically gate-all-around nanowire architecture (EGAA NW) with much reduced parasitic capacitance and increased effective width for better short channel control and stronger drive. We suggest SiGe P-channel by Ge Condensation for intrinsic mobility improvement and substrate strain, conformal...
Advanced CMOS nodes target high-performance at lower supply voltage. High-mobility III-V channel materials have the potential to meet this target. Although III-V materials such as InGaAs are beneficial for nFET channels, SiGe (or Ge) provides better hole mobility and is more suited for pFET channels. Therefore, a InGaAs/SiGe hybrid CMOS technology is being pursued for scaled nodes. There are significant...
A tunable PNP-based ESD clamp is designed for a 4.5V power IO in a foundry technology. Using Mixed-Mode TCAD simulations, we show that the clamp's trigger and holding voltage can be easily tuned by simple layout modifications. The fabricated clamp was characterized using an on-wafer TLP system, confirming the tunable Vt1=13.4−16.8V, with Vhold slightly above 10V and It2>1.2A. Finally, the clamp...
For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated...
SRAM paves the way for new technology nodes as it is more prone to failure due to intrinsic devices variability and technology process. To further boost high density SRAM yield and performance we need assist techniques and increased SRAM bit cell size at the expense of area. This paper discusses SRAM design strategies for future technologies nodes like beyond the N7 node, by comparing higher height...
Here, we report the development of an integrated sensing platform for the field of assisted reproductive technologies (ART), and more specifically for the pre-implantation culture of mammalian embryos and their in situ characterization through evaluation of their metabolic activity. The entire platform consists of a nanoliter-culture chamber, with an integrated oxygen sensor to monitor the respiratory...
The proof of concept of a new extended-gate pH sensor, developed on an industrial ultrathin body and buried oxide (UTBB) fully-depleted silicon-on-insulator (FDSOI) transistor, is reported. The strong electrostatic coupling between the front gate and back gate of UTBB FDSOI devices provide a signal amplification opportunity for sensing applications. On the other hand, the biasing capability through...
Here, the utilizing of lateral unidirectional bipolar-type insulated-gate transistors (Lubistors) for pH detection was demonstrated for the first time. The high on current and ambipolarity of Lubistors are favorable properties for reliable sensing application. The ultrathin Lubistors were fabricated on 20-nm-thick SOI substrates in planar geometry. The triode-like current-voltage characteristic and...
Based on a novel approach of reading-out cantilever sensors with an exponential response of the measurement signal on adsorption of e.g. molecules, we study cantilever array sensors that enable the detection and discrimination of various different adsorbates. Different cantilever geometries and different ratios of functionalized and unfunctionalized areas on the cantilevers are used together with...
Amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) Thin-Film Transistors (TFTs) integrated with Si based CMOS processes is an emerging technology in ultra-low power applications. ESD characteristics of a-IGZO TFTs with a Si substrate are studied and compared to their characteristics on traditional foil/glass substrate. The ESD performance is shown to be improved, thanks to improved thermal properties of...
Recent research progresses on dopant diffusion and segregation, Si-Ge interdiffusion and defect engineering in SiGe material systems are reviewed, which are relevant to SiGe-based semiconductor devices including SiGe PNP hetero-junction bipolar transistors, metal-oxide-semiconductor field-effect transistors, and Ge-on-Si lasers. Experiment data and continuum modeling are discussed.
The hysteresis in the gate transfer characteristics of transistors made of two-dimensional materials is one of the most obvious problems of this novel technology. Here we attempt for the first time to develop a physical modeling approach for describing this hysteresis in devices based on two-dimensional materials. Our model is based on a drift-diffusion TCAD simulation coupled to a previously established...
Device modelling is a key enabling capability for the semiconductor industry, especially for process optimisation, and for insight into the physics of novel architectures and materials that are difficult to access experimentally. Despite much innovative experimental work, device modelling capabilities for field effect devices based on Transition Metal Dichalcogenide (TMD) channel materials are at...
Channel thickness Tch dependence of electron mobility μκρρ in thin In0.53Ga0.47As channels was investigated at temperatures T from 35 to 300 K using conventional parametric and pulsed ID-measurements, including a novel technique with time resolution down to 10 ns. It is show that accurate mobility measurements can be obtained using low T and/or fast pulsed measurements, thus avoiding significant underestimations...
A small amount of slow trap density in Ge gate stacks is a crucial issue for Ge CMOS, in addition to thin equivalent oxide thickness and low interface state density. In this paper, we study the slow trap position and the generation mechanism in the high-k/GeOx/Ge interfaces fabricated by plasma oxidation. The slow trap density in Al2O3/GeOx/Ge interfaces by plasma pre-oxidation is compared with different...
In this work, the electrical isolation of nanowires fabricated on bulk wafers is investigated. It is shown that electrical isolation can be realized with a Ground Plane isolation implant at the beginning of the process flow. For transistors using extensions, it is seen that a relatively high dose of Ground Plane doping is needed in order to avoid punchthrough through a parasitic channel less controlled...
In this paper the operation mechanism of ambipolar Si-nanowire (Si-NW) Schottky-barrier (SB) FETs is discussed in detail using temperature dependent current-voltage (I-V) contour maps. Thermionic and field emission mechanism limited the overall conduction behavior of ambipolar Si-NW SB-FETs with considerable SB-height. However, Si-channel dominant transports with phonon scattering mechanism occur...
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