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A novel BSC circuit with tunable current starved buffers demonstrates higher sensitivity, scalability & accurate statistical characterization of radiation-induced SET pulse waveforms & flip-flop SER in 14nm tri-gate CMOS, thus enabling improved SER estimation & analysis for a range of supply voltages including NTV.
Progressive impacts of aging on Fmax & noise margin of the precharge-evaluate domino read, and VMIN for differential static write & retention are demonstrated via statistical measurements over the operational lifetime of a 14KB 1R1W 8T SRAM array in 22nm high-k/metal-gate tri-gate CMOS.
To optimize the classic design trade-off between EMI noise and power efficiency in GaN power drivers at 10MHz and beyond, a closed-loop adaptive Miller Plateau sensing (AMPS) technique is proposed. In order to mitigate long delays and low accuracy issues in conventional Miller Plateau (MP) sensing approaches, an emulated MP tracking (EMPT) technique is adopted to achieve instant MP start point sensing...
This paper proposes a pulse-tail-feedback technique for improving both 1/f2 and 1/f3 noises. The proposed VCO has separated tail transistors driven by inverters with rail-to-rail voltage swing. The tail transistor has an impulse shaped current waveform to improve FoM, and the flicker noise up-conversion is reduced by the switching operation. A prototype of the proposed VCO is implemented in 180nm...
A CMOS on-chip oscillator (OCO) for local interconnection network (LIN) bus is presented. The temperature dependence of the output frequency is compensated by the voltage ratio adjusting (VRA) technique. The frequency variation with supply voltage is reduced by a voltage regulator with a wide input range of 1.8 V to 5.0 V. The frequency shift caused by package stress is minimized by resistor placement...
This work proposes an all digital clock generator (ADCG) with a new PVT compensation technique to generate a stable and accurate frequency over wide frequency ranges up to 8GHz. To compensate frequency variations by temperature changes, a novel Zero Temperature Coefficient (ZTC) algorithm using mutual compensation between the mobility and the threshold voltage of devices has been implemented. The...
We propose a new approach to an on-chip clock distribution scheme. It is based on distributed multi-GHz LC-tank oscillators generating local clocks. The oscillators are mutually coupled to align their frequencies and are further subharmonically injection-locked to a much lower frequency reference to align their phases. The final phase calibration is via adjusting their self-resonant frequencies. We...
An LC-VCO-based MDLL is presented in a fractional-N frequency synthesizer to extend its frequency multiplication factor and performance. By employing the proposed MUXs in the LC-VCO, it increases the loop bandwidth (BW) from 3MHz to 15MHz (nearly 0.4fREF) as well as flicker noise suppression. Moreover, the re-quantized delta-sigma modulator (DSM) is combined with the prototype in order to reduce spurious...
This paper presents a new dynamic residue amplifier for pipelined ADCs. With an input of 100mVpp, diff and 4x gain, it achieves −100dB THD, the lowest ever reported in dynamic amplifiers. Compared to the state-of-the-art, it exhibits >25dB better linearity with >2x larger output swing and similar noise performance. The key to this is a new linearization technique based on capacitive-degeneration...
A hybrid power amplifier (PAhybrid), combining class-D and class-AB amplifier is demonstrated. As a specific structure for class-D, 3-level and 3-phase (3P3L) techniques are applied to reduce the current ripple to 1/12th of that of standard 2-level class-D amplifier. At the same time, the effective switching frequency increases by 6 times. Compared to the previous works which use several uH inductors,...
This paper presents a highly power efficient amplifier. By stacking inverters and splitting the capacitor feedback network, the proposed amplifier achieves 6-time current reuse, thereby significantly boosting gm and lowering noise but without increasing power. A novel biasing scheme is devised to ensure robust operation under 1V supply. A prototype in 180nm CMOS has 5.5uV rms noise within 10kHz BW...
For the first time, complex conjugate poles are integrated on silicon by using only switches and capacitors. A general design methodology is proposed to implement low-pass transfer functions with sharper frequency profile compared to the passive-switched-capacitor topologies present in the literature. Theory and simulation results are validated through the measurements of a 0.13μm prototype filter...
This paper presents a low-power, high-PSRR sub-bandgap voltage reference that operates under 1V supply. In order to achieve low temperature coefficient (TC), a CTAT circuit with internal feedback and a two-transistor PTAT circuit are proposed. For improved line sensitivity (LS) and PSRR, a self supply-regulated feedback is employed. Implemented in 0.18μm CMOS, the proposed voltage reference achieves...
A fully integrated digitally controlled buck VR, featuring hysteretic and PFM control for maximum light load efficiency, with 3D-TSV based on-die solenoid inductor with backside planar magnetic core in 14nm tri-gate CMOS demonstrates 111 nH/mm2 inductance density & 80% conversion efficiency.
A 6Gb/s 9.8pJ/b rotatable non-contact connector applicable to robot arms is developed. The proposed rotatable transmission line coupler (RTLC) has a wide bandwidth at all rotation angles. An interface bridge IC is also developed to transfer a wide range of interface signals from slow legacy ones to high-speed ones. The proposed system improves power efficiency by a factor of 3.7, space efficiency...
A micro-bolometer focal plane array (MBFPA)-based long wavelength Infra-red thermal imaging sensor is presented. The proposed multiple digital correlated double sampling (MD-CDS) readout method employing newly designed reference-cell greatly reduces PVT variation-induced fixed pattern noise (FPN) and as a result features much relaxed calibration process, easier TEC-less operation and Shutter-less...
An energy-efficient and high-speed stereo matching processor is proposed for smart mobile devices with proposed stereo SRAM (S-SRAM) and independent regional integral cost (IRIC). Cost generation unit (CGU) with the proposed S-SRAM reduces 63.2% of CGU power consumption. The proposed IRIC enables cost aggregation unit (CAU) to obtain 6.4× of speed and 12.3% of the power reduction of CAU with pipelined...
A 4+2T SRAM is proposed that offers searching and logic functions. The cell uses the N-well as the write wordline (WL) and eliminates the access transistors. Decoupled read paths enable reliable multi-word activation for in-memory Boolean logic functions. The SRAM can reconfigure to BCAM/TCAM for searching operations, with 0.13fJ/search/bit at 0.35V. Forty test chips in 55nm deeply depleted channel...
An embedded 1 Mbit 2T1C gain-cell memory macro using indium-gallium-zinc oxide semiconductor FETs (OSFETs) with an extremely low off-state current of less than 1 zA (10−21 A) was fabricated. In the 2T1C gain cell, an OSFET for the write operation was stacked over a SiFET for the read operation. The 1 Mbit macro was fabricated using a combination of 60-nm OSFET and 65-nm CMOS processes. It achieves...
Recent embedded ReRAM has a small resistance-ratio (R-ratio), which results in a small read sensing margin (ISM). A larger BL current (IBL) increases the input offset (IOS) of current-mode sense amplifiers (CSA), resulting in low-yield read operations and long read access times (TCD). This work proposes an IBL-aware small-IOS CSA, using a dynamic trip-point-mismatch sampling (DTPMS) scheme to increase...
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