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A 4 MHz monolithic digital single-inductor dual-output (DSIDO) buck/boost converter based on 10-bit ΣΔ modulator and 4-bit delay line digital pulse width modulator (DPWM) is presented. Window delay line ADCs, digital PID compensator and DPWM with 2nd ΣΔ modulator are utilized in the converter to pursue highly flexible and intelligent power management. Digital Extend PWM control method is proposed...
A newly structured 150GHz divider-by-2 injection-locked frequency (ILFD) is designed in a 65-nm CMOS technology. This ILFD uses a new adjustable inductor tuning technique and time-interleaved dual-injection method to improve the frequency division range. A 1-bit binary-weighted switch-capacitor is also used to widen the locking range. From the post-layout simulation result we can see that four self-resonance...
In this paper, an intelligent and low power EEG(electroencephalograph) processing multi-QOS(quality of service) DSP has been designed with the smicrf180nm technology used for EEG wearable Instrument. The bio-detection uses the Ag/Ag-Cl electrode sensor to extract the head skin's micro EEG signal, and uses the differential chopper-LNA circuit to cancel the 1/f, dc-offset voltage and other noises. On...
This paper describes the design of a fully-integrated PLL-based and integer-N quadrature frequency synthesizer (QFS) for Ka, V and E multiband mm-wave applications. A 2-bit switched capacitor array directly controlled by voltage level together with MOS varactor and differential coplanar waveguide (CPW) inductors are used in the quadrature voltage-controlled oscillator (QVCO) to cover the wide frequency...
A portable counter-assisted all-digital phase-locked loop (ADPLL) with fast settling time is presented in this paper. A wide-frequency-range and high-resolution interpolating digitally controlled oscillator (IDCO) is proposed to satisfy target frequency requirements. Three settling processes with different kinds of loop filters enable both fast settling time and low jitter. The proposed ADPLL has...
A 12.5Gbps quarter rate SerDes CDR for high speed serial link communication is presented in this paper. The proposed dual loop structure consisting of frequency tracking loop and phase tracking loop has good input jitter rejection. A novel dual switching ppms lock detector is proposed to ensure proper switching of dual loops to prevent false locking. Moreover, a novel quarter rate bang-bang phase...
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