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This paper presents a 24.25–26.65 GHz 6-bit phase shifter in 65nm CMOS technology. The proposed architecture of the phase shifter divides the 6-bit phase shifter into one 3-bit and three 1-bit sub phase shifters. The low resolution sub phase shifters can be implemented just by switches and sub VGA cells which can lower the phase error apparently. The phase shifter results in a simulated RMS phase...
Self-organizing map (SOM) is an important statistical method for cluster analysis. The conventional single instruction multiple data (SIMD) solution sufficiently exploits the massive intrinsic parallelism of artificial neural networks. In this paper, we introduce a parallel-elementary-stream (PES) architecture for nearest-neighbor-search (NNS) based SOM model as an alternative to SIMD. The PES defines...
Motivated by reduction of computational complexity, this work develops a pipelined adaptive filter architecture using the sign-error least mean square (SELMS) algorithm. The proposed algorithm was implemented with less than half the amount of calculation consumed for the conventional architectures. Besides, the proposed designs derived by retiming technique and with low latency also provide a faster...
The TSV(Through-Silicon Via) plays an important role of inter-layer interconnection in 3D ICs. However, TSV is defect prone. This paper proposes a new scheme based on oscillator to monitor the defects of TSV at the prebond stage.
The impact of polysilicon thickness (THK-poly) and channel hole diameter (CHCD) on channel boosting potential during program inhibit has been studied with Sentaurus device simulator for three dimensional (3D) NAND memory. According to the distribution of boosting potential along the channel, the potential level of thinner THK-poly is higher than that of thicker one. Moreover, the correlation between...
In this paper, a dual-field elliptic curve cryptographic processor is proposed to support arbitrary curves within 576-bit in dual field. Besides, two heterogeneous function units are coupled with the processor for the parallel operations in finite field based on the analysis of the characteristics of elliptic curve cryptographic algorithms. To simplify the hardware complexity, the clustering technology...
In this paper, a high-flexibility and energy-efficient reconfigurable symmetric cryptographic processor architecture is presented, which is based on very-long instruction word (VLIW) structure. By analyzing basic operations and storage characteristics of symmetric ciphers, the application-specific instruction-set system for symmetric ciphers is proposed. Eleven kinds of reconfigurable cryptographic...
High-Bandwidth Digital Content Protection(HDCP)-it is a technology method which is used to protect the high definition signs. This paper focuses on design and verification of authentication part, the most important of a HDCP2.2 transmitter. Besides architectural analysis and design approach discussions, a detailed micro architecture, including signature verification, key encryption and revocation...
This paper presents the implementation of CRC-16 on a novel FPGA, a collection of reconfigurable operators (ReOps), which has smaller configuration bits-stream and better performance than traditional FPGA. A ReOp is a basic block which can process multiple bits data with a specific function set. Considering the complete function set of ReOps, we divide ReOps into eight groups: Arithmetic ReOps, Multiplier...
A wideband and high linearity IF programmable gain amplifier (PGA) is presented for 60GHz wireless receivers. The core of the circuit is a differential amplifier based on the “flipped voltage follower” (FVF) cell. The FVF cell introduces an additional zero and extends the bandwidth without extra power consumption. The presented PGA has been implemented in 65nm CMOS, and the simulation results show...
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