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In near-threshold multi-voltage designs, large clock skew occurs between different voltage domains. Several works of power-mode-aware buffer (PMAB) were dedicated to diminish this clock skew. However, they were commonly based on circumstances that each power domain had at most two supply voltages. In this brief, we propose a multi-stage PMAB approach to diminish clock skew for multi-voltage multi-power-mode...
Low-power VLSI circuits are indispensable for almost all types of modern electronic devices, from battery-driven mobile gadgets to harvested-energy-driven wireless sensor systems. However, the testing of such low-power VLSI circuits has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper will highlight three major test-power-induced problems (namely...
Self-organizing map (SOM) is an important statistical method for cluster analysis. The conventional single instruction multiple data (SIMD) solution sufficiently exploits the massive intrinsic parallelism of artificial neural networks. In this paper, we introduce a parallel-elementary-stream (PES) architecture for nearest-neighbor-search (NNS) based SOM model as an alternative to SIMD. The PES defines...
This paper presents a power-efficient 100-MS/s, 10-bit asynchronous successive approximation register (SAR) ADC. It includes an on-chip reference buffer and the total power dissipation is 6.8 mW. To achieve high performance with high power-efficiency in the proposed ADC, bootstrapped switch, redundancy, set-and-down switching approach, dynamic comparator and dynamic logic techniques are employed....
This paper presents a 7.9 fJ/conversion-step 10-bit 125 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) on the basis of a monotonic capacitor switching procedure. Simplified power-efficient digital control logic, multi-layer sandwich capacitor structure and high-speed level-shift bootstrapped sampling-and-holding (S/H) blocks are employed to achieve high performance...
Low power design is critical in today's chip design. Clock tree takes much of chip power. “Clock tree cost” is introduced to help design low power clock tree. Five methods are proposed to reduce “clock tree cost” and improve clock tree efficiency. They include clock sink depth check, redundant scan mux check, redundant clock gating cell check, CCOPT (Clock Concurrent Optimization) and simple clock...
This paper provides several methods by using Synopsys IC Compiler (ICC) to optimize Clock Tree Synthesis (CTS), reasonable floorplan, parameter constraint, manual specification, Engineering Change Order (ECO) included. An IC smartcard named BES1300 using 0.18µm EFLASH 2P4M technology is applied to verify the propose methods. Optimizing timing manually is mainly described. Testing results show that...
This paper presents a directly triggered asynchronous successive approximation register (SAR) logic with variable delay unit. With the help of the designed logic, the CDAC can be settled directly by the comparator result that avoids long propagation delay as conventional SAR logic does. Moreover, a variable delay unit is designed which provides more settling time to the last several bits to get more...
In traditional pipelined ADCs, errors originated by capacitance mismatch, finite amplifier gain, incomplete settling and offset. To overcome capacitance mismatch for >=2.5-bit/stage MDAC architecture, a new background digital calibration strategy is proposed in this paper. Based on this technique, a 14-bit, 40MS/s pipelined ADC is implemented. The simulation results show that ENOB is improved from...
As the technology scales down, the single-event transient (SET) has become a great concern for the reliability of integrated circuits (ICs). A novel time redundant flip-flop structure is proposed to detect and correct the SET pulse. The most advantage of this structure is that it has very little setup and hold time overhead and the architecture need not be modified to recover the system. HSPICE simulation...
High-Bandwidth Digital Content Protection(HDCP)-it is a technology method which is used to protect the high definition signs. This paper focuses on design and verification of authentication part, the most important of a HDCP2.2 transmitter. Besides architectural analysis and design approach discussions, a detailed micro architecture, including signature verification, key encryption and revocation...
In this paper, a reliable and clear clock architecture and execution scheme is illustrated for the direct broadcast satellite set-top-box HD-SOC IC chip. To solve the stable and flexible clock/reset signals' generation and to satisfy the chip's debug/test bypass control, this paper gives a robust and flexible clock network realization. Also, the whole HD-SOC is manufactured with the TSMC90nm technology...
Process variation results in up to an order of magnitude variation in Ion/Ioff ratios, which significantly depresses the yield of the sub-threshold circuits. This paper presents low power sub-threshold adders using sense amplifier-based pass transistor logic (SAPTL). Based on the simulations in 130nm CMOS process, the proposed two-phase synchronous SAPTL adder exhibits stronger robustness to process...
A 12-bit 250MSPS Pipeline ADC with serial output interface is presented. The pseudo random (PN) calibration technique is used to improve the dynamic performance in the high speed ADC. A integrated serial output interface is implemented to convert 12 bit parallel data into a differential serial data stream. The whole pipeline ADC was fabricated in 180nm 1.8 V 1P5M CMOS process. Test results show that...
K-nearest neighbor (KNN) classification algorithm performs slowly for large scale training set and high dimensions. To overcome the disadvantage, we need to focus on the points within a predetermined range, without changing the precision. This method is named Predetermined Range Search (PRS). In this paper, we proposed a method to find the reference distance (ReDist), a parallel and pipelined architecture...
This paper presents a wireline communication receiver with merged continuous-time linear equalizer (CTLE) and decision feedback equalizer (DFE) summer circuit. The merged circuit removes the traditional CTLE and merge it into the following DFE summer to builds linear equalization so as to significantly reduce the receiver power consumption. Analysis for the conventional equalizer and proposed circuit...
The Ziggurat algorithm is an efficient way for building a Gaussian random number generator (GRNG), which is useful in many scientific and engineering applications. As the classic ziggurat-based GRNG includes nonlinear operations in judging the wedge and tail regions, which is complicated and resource consuming. An improved ziggurat algorithm is proposed by optimizing the accepting model with piecewise...
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