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In this article, we demonstrate plasma-enhanced atomic layer deposition (PEALD) as an effective passivation technique to establish high interfacial quality of high-k/InGaAs structures. Performing PEALD-AlN as an interfacial passivation layer (IPL), excellent capacitance-voltage (C-V) characteristics have been achieved for the HfO2/n, p-In0.53Ga0.47As MOSCAPs. The effects of AlN-IPL on the effective...
We present a novel design of bulk transmit-receive (T/R) switch FET to reduce switch loss and harmonics. Along with this we present an improved low-noise amplifier (LNA) bipolar design in a 350nm SiGe BiCMOS technology for providing better WiFi RX path performance in 802.11ac wave-2 applications. Tighter lithography aspects of 180nm is utilized to make these critical performance advancements.
In this paper, we first analyze an LNA core, cascode structure cut off frequency and power gain relationship with device parameters. Then we discuss the LNA design differences between FET LNA and SiGe LNA during design optimization. SOI floating body FETs have advantages in higher Ft in the optimized current biased region and can offer more design flexibility, while SiGe NPNs need much less trade...
A low phase noise voltage-controlled oscillator for mm-wave applications is presented. The oscillator uses switched-capacitor technique to increase the tuning range. The measured results show that the oscillator achieves a phase noise of −100dBc/Hz at 1MHz offset from the carrier frequency of 49.7GHz, while consuming 5.5mA current from a 0.9V supply. A wide tuning range percentage of 12%, i.e. 43...
A possible strategy for the characterization of grown-in and processing-induced electrically active point and extended defects in high-mobility substrates is presented and illustrated by examples obtained on Ge as a prototype system.
Electron mobility has been characterized for drain current simulations of AlN/GaN MIS-HEMTs. We especially focus on the embedded source field-plate structures (ESFP) for high power applications. To apply the models to simulate power switching applications including DC-DC converters, electron mobility equations are the key to characterize DC bias conditions under dynamic operations. The model is implemented...
A 2.4GHz Doherty power amplifier (DPA) using capacitance compensation is proposed in 0.18um TSMC process. Doherty configuration with self-biased cascode transistors is adopted to achieve high output power and efficiency in power back-off region. The lumped element π-network is employed to replace the quarter wave transmission lines and facilitates the integration. Placing the PMOS device in parallel...
The application of carbon-nanotube to reduce interconnect delay is studied in this work, with the emphasis on how it can be used to reduce the inter-metal capacitance. By forming vertically aligned cylindrical pores assisted by vertically grown CNT, mechanically stable ultra-low-k interlayer dielectric with k-value down to 1.89 is experimentally demonstrated. Ways to integrate this process will other...
This paper presents a new structure of column-level successive approximation register (SAR) analogue-to-digital converter (ADC) for Infrared Focal Plane Array. In this design, each column has a capacitance array and each comparator and SAR logic block are shared by 8 columns. By using this shared structure, we achieved smaller silicon area, lower power dissipation and lower noise. And shared structure...
In this paper, a semi-analytical model for the gate-to-source/drain fringing capacitance (Cf) of MOSFET including process variations is presented. Cf is defined as a layout-dependent parasitic capacitance separated from gate-to-contact capacitance (Cco), and is composed of several dual-k perpendicular-plate capacitances. Layout-dependent coefficients such as gate to contact space (CPS) and contact...
In traditional pipelined ADCs, errors originated by capacitance mismatch, finite amplifier gain, incomplete settling and offset. To overcome capacitance mismatch for >=2.5-bit/stage MDAC architecture, a new background digital calibration strategy is proposed in this paper. Based on this technique, a 14-bit, 40MS/s pipelined ADC is implemented. The simulation results show that ENOB is improved from...
TSV (Through-silicon Via) meets the demands of high speed and low power consumption in 3D integrated circuits. However it faces challenge in signal integrity problem such as crosstalk. TSV to TSV coupling is the most significant crosstalk problem in TSV based 3D ICs. This paper presents a quantitative estimation on the TSV to TSV crosstalk induced interconnect delay, trying to find the worst interconnect...
Designing and fabrication of 4kV, 20A 4H-SiC PiN diodes with JTE junction termination structure have been investigated in this paper. A bevel mesa structure and a single-zone junction termination extension (JTE) have been employed to achieve the target voltage. Finally, an optimized mesa structure without sub-trench (mesa height of 2.2 µm and mesa angle of 20°) has been experimentally demonstrated...
Transient capacitance measurement is used to study the trap behaviors in AlGaN/GaN MIS-HEMTs: 1) By measuring transfer characteristics before and after the pulse cycles applied on the gate electrode in AlGaN/GaN MIS-HEMTs, the threshold voltage (Vth) instability induced by the gate pulse is investigated; 2) The change of trap density before and after step-stress applied on drain electrode is also...
Capacitance-voltage (C-V) characteristics have been measured in this paper to calculate the depth profiles of GaN carrier concentration in four different structure GaN-based HEMTs, revealing the consequences of Al2O3 oxide layer and etching depth on two-dimensional electron gas (2DEG) sheet density. Combining the energy band diagrams with the theoretical calculation formula of 2DEG, we analyzed corresponding...
A low turnoff loss (Eoff) silicon-on-insulator lateral insulated gate bipolar transistor with p-buried layer and double gates (DG-PB SOI LIGBT) is proposed. The proposed LIGBT features a p-buried layer (PB) in the n-drift region and an additional trench gate. Due to the large capacitance effect and hole extraction path induced by PB, larger number of the carriers is removed under low anode voltage...
The shallow junction is used in the PDSOI technology. Unfortunately, the standard diode model maybe not suit to this PN junction. A simulation model is proposed based on the PDSOI process. The additional influence of the voltage bias of the junction to the capacitance is considered in this model and then the model is well verified by the measured data.
For low cost and high integration, an on-chip compensator implemented in a Buck converter with minimized external pins and high performance is proposed. Trans-conductance amplifiers with constant Gm and high linearity are developed to substitute the resistors; meanwhile capacitance multipliers consisting of high-gain amplifiers are designed to replace the capacitors. Thus, all passive devices in compensator...
An Operational Transconductance Amplifier (OTA) with a novel dynamic-output control technique is proposed to achieve high slew rate (SR) performance in this work. The dynamic-output control technique utilizes two subtracters controlling the current sources to sink or source the output load adaptively. Moreover, as additional current sources are disabled in the DC operation status, the proposed structure...
In this Paper, a fractional-N frequency synthesizer fabricated in a 0.18µm process is designed for a FSK transceiver. The precision of the charge pump can be improved by exploiting the op amplifier. Based on capacitance multiplication technique, the area of loop filter is reduced. The fractional-N divider function is realized by the sigma delta modulator. FIR filter is designed in the input stage...
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