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This paper proposes a 500V U-shaped channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual trenches to improve the trade-off between the saturation voltage (VCEsat) and the turn-off loss (Eoff). The proposed dual trenches U-shaped channel (DTU) SOI-LIGBT features a U-shaped gate trench (Gl) and a U-shaped hole barrier trench (G2). By employing the dual trenches,...
This paper proposes a novel LDMOS structure with ultra-shallow trench isolation (USTI) and p-buried layer in 0.18um BCD technology platform. This platform offers 18V to 40V LDMOS devices which has best-in-class specific on-resistant (Ron, sp) with respect to similar technologies. USTI structure is implemented in LDMOS drift region to reduce specific on-resistance (Ron, sp) by shortening the current...
The Ron sp of a DMOS operated at high side (Ron_sp_HS) in the power management ICs is usually underestimated by taking the measured value at low side operation (Ron_sp_LS). The Ron_sp_HS is increased drastically when a revise voltage is applied between drift region and substrate because the drift-region is depleted and the current path is narrowed. In this paper, a novel structure with a varying-junction-depth...
Shielded-gate trench or “Shield RESURF (REduced SURface Field)” MOSFETs have been well known for its lower RDS(ON) ×Area, and lower Rds(on)×Qgd figure of merits (FoMs), and used widely in the low to medium voltage applications (25 V to 200 V). However, this improvement is achieved at the expense of higher output capacitance or output charge (Coss or Qoss), which has become an increasingly important...
We have proposed the concept of thin layer SOI devices with stepped field plates to obtain a low on-resistance LDMOSFET. Thin layer SOI devices can acquire a high breakdown voltage because the ionization integral over the vertical path may be neglected. A doping concentration in a drift region of a thin layer SOI device can be increased by reducing the thickness of the surface oxide. This is because...
This paper demonstrated a novel LDMOS with gate-connected shielding-contact structure, no extra mask or process is needed. TCAD simulation reveals lower electrical potential and impact ionization with the proposed structure. Ron-sp/BVD ratio reduction and significant HCl SOA improvement have been verified on real Silicon. Newly layout with Slot-Poly design has been investigated for better process...
A new 600V SOI shorted-anode LIGBT with multi-segment anode (MSA) is proposed and investigated in this paper. The device features a multi-segmented P+ anode and p-buried layers (PBL) formed in both anode and cathode regions. The combination of MSA and the PBL below the anode increase the anode distributed resistance (Rsa) and effectively suppress snapback effect with small dimensions in both x- and...
This paper presents three-dimensional (3-D) edge termination design of a 700-V triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with n-type top (n-top) layer. It is found that breakdown characteristics deterioration related to the electric field crowding and the local charge imbalance in the edge termination. The two crucial parameters LP and L2 in the layout of the transition...
A novel DTI double RESURF LDMOS with P-sink layer is presented and experimentally demonstrated in this paper. The novel structure features a P-sink layer around the bottom of deep trench, which is formed with the Deep N-type Well (DNW) after the process of high temperature driving in. The highly doped P-sink layer restrains the extension of depletion region along the horizontal direction, improving...
This paper proposes a simple and efficient method to improve hot carrier (HC) immunity of p-channel LDMOSFET without degrading typical figure of merits such as breakdown voltage BV and specific on-resistance Rsp. The superiority of a novel STI-based p-channel LDMOSFET with a hot electron cooling (HEC) layer against the conventional method to improve HC immunity (i.e. extending the p-drift length)...
A trench/planar MOSFET (TP-MOS) is proposed in this work as a high speed switching device. The device is comprehensively studied with numerical simulations, and comparisons are made with the conventional MOSFET (C-MOS) and the split-gate MOSFET (SG-MOS). Compared to the C-MOS, the removal of the MOS-structure above the JFET region results in a dramatic reduction of the reverse transfer capacitance...
A new kind of field plate as contact field plate is fabricated for hot carrier injection improvement, significant decrease in the specified on resistance degradation is observed without substantially affecting the breakdown voltage of devices. Charge pumping method and simulation are carried out to study the degradation mechanism. Our results clearly show that the application of contact field plate...
A novel concept for a BCD technology is presented which comprises the processing of the wafer on the thinned backside and which offers — similar to SOI technology — a full dielectric isolation of power devices. Limitations of the breakdown voltage of p-LDMOS encountered in conventional BCD technologies are overcome by replacing the commonly applied deep n well layer by an n+ region formed on the wafer...
In this paper, a 13-kV SiC MOSFET with a retrograde doping profile in junction field-effect transistor (JFET) regions, which were implanted by nitrogen ions with multiple energies, has been developed for power supplies of X-ray generators and electron guns with an accelerating voltage greater than 10 kV. A JFET region was optimized with device simulation to reduce on-resistance. A SiC MOSFET with...
Passivation films on the termination area of 4H-SiC diodes were investigated to clarify the origin of a positive charge accumulation that induces instability of the breakdown voltage. A method to differentiate measured depletion layer capacitance is proposed as a way to analyze the positive charge density after applying voltage stress. Samples with different passivation films were fabricated to compare...
In this paper, a simple self-aligned process for defining short channels in 3.3-kV SiC DMOSFETs is presented and designed using a TCAD simulation. The proposed process involves channel definition by Al ion implantation at a tilted angle through the source mask and eliminates the complicated hard mask etching process. The simulation results show that implantation of 1× 1013 /cm2 and 450 keV at a 30°...
In this paper we introduce a new generation of silicon carbide (SiC) Schottky diodes with reduced threshold voltage. A detailed comparison with Infineon's 5th generation of SiC diodes (G5) is done. With a Mo-based Schottky metal system, the new generation of diodes (G6) was designed in such a way that the increased reverse power loss is more than balanced by the efficiency gained by the low threshold...
In this work, a useful interfacial damage extraction method for SiC power MOSFETs based on the C-V characteristics is proposed. According to the five different interface situations of the channel region and the JFET region, the Cg-Vg curve can be divided into five relatively independent parts. It demonstrates that the charges injected into the oxide of channel region will lead to an opposite shift...
This paper focused on the investigation of short-circuit capability and failure mechanism for the commercially available SiC trench MOSFETs. There are three failure mechanisms; (1) avalanche generation, (2) thermal runaway and (3) breakdown of gate oxide layer between gate-source electrodes by different short-circuit conditions. These are dependent upon the drain voltage and, especially in the high...
The evaluation of power cycling results needs correct measurement of the course of thermal resistance. Hence an accurate online measurement of the junction temperature is necessary. Different measurement and power cycling methods were evaluated. The method of measuring the voltage drop of the SiC MOSFET body diode pn-junction at low measurement current with sufficient negative gate-voltage was found...
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