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The impact of temperature (T) on BTI time slope (n) and voltage acceleration (VAE) in MGHK planar and FinFETs are discussed here. Steeper time slopes and higher VAE are observed at lower 1/kT for thin gate oxide devices across different stress voltages. Dual time slope behavior in planar thick oxide PFETs is observed. Time slopes increase as sense delay is increased for lower 1/kT while a reverse...
We characterize the critical peak current which causes melting of Cu/low-k interconnects under short-pulse conditions. High-current with 100ps pulse width is achieved using an on-die pulse generator A model incorporating the heating of the metal layer and heat diffusion through the insulator layer is supported by the experimental results. The model accurately describes the relationship between peak...
Ferroelectric tunnel junctions with ultra-thin Y-doped HfO2 film was investigated for the low power, high speed, non-volatile memory. Polarization switching-induced resistance change amounts to ∼100 in the on/off ratio. The electrode area-dependent current and no need of the forming process show a striking contrast to the filament type of ReRAM. FTJ memory with ferroelectric HfO2 will provide us a...
For the first time, analytical equations for skin and proximity effects are derived to successfully describe current distributions in advanced CMOS technology interconnects subject to high-frequency signals. The analytical solution matches simulations evaluating skin depth as a function of interconnect geometry and operating frequency.
Integrated Circuit (IC) was invented in 1958 in the process of challenges to “Tyranny of Numbers”. We face the same challenge again with the end of Moore's Law and rise of IoT. A near-field coupling integration technology (Fig.1) is proposed as a new solution in very large system to replace mechanical connections by electrical ones. This paper presents two technologies. ThruChip Interface (TCI) replaces...
Low temperature wafer scale direct bonding technology using plasma activated bonding (PAB) for heterogeneous photonic device integration is reviewed. Nitrogen plasma irradiation in a high vacuum chamber allows tight strength bonding between InP-based and SOI wafers with the bonding temperature of 150°C as well as low damage to GaInAsP quantum wells (QWs). In contrast Argon irradiation cause poor bonding...
We have developed a novel packaging tool-set of 13 machines to support continuous manufacturing process from a half-inch wafer process line until ready to be used. The packaging tools are made under minimal fab standard so that a half-inch wafer can be attached on a metal-substrate without dicing. The method that we employed is a BGA (Ball Grid Array)-type solder array which consists of following...
Electrodeposited cobalt has received significant attention in recent years as a suitable metallization alternative for many interconnect technologies. For instance, Co is being evaluated as back-end-of-line (BEOL) alternative for Cu in 10 nm node technologies due to challenges with scaling the diffusion barrier at small CDs and increasing electron scatter in small features [1]. A super-conformal Co...
This talk will go over the various considerations that lead into final selection of a package for a particular application and end form factor. These aspects not only include cost and performance requirements but also include die constraints and OEM PCB choices. It will show an example that for different tier of phones; these trade-offs are different which leads to unique package selection choices...
Atomic layer deposition (ALD) is widely in use for depositing a variety of materials, such as metal oxides, metal nitrides and metals, in a conformal and defect-free form at low temperatures on high aspect-ratio substrates. These advantages make ALD uniquely powerful method for applications where sensitive substrate materials combine with extreme demands on coating quality and temperature/chemical...
CVD and more recently ALD have become methods of choice for the deposition of new materials, to deal with the 3D nature of new devices, and to meet the requirement for atomic level thickness control. Several examples illustrate how precursor design can contribute to keeping the cost of new materials deposition in control, whether through easier facilitization thanks to better physical properties,...
We describe the effect of microwave heating on C3H5 carbon cluster ion implanted epitaxial wafers using a high dose amount of carbon cluster ion implantation condition. A high dose amount condition of C3H5 carbon cluster ion implantation generates implantation-related defects, such as stacking faults, after epitaxial growth. Therefore, we investigated the control and reduction of stacking faults using...
Interstitial trapping by oxygen-inserted silicon channel results in blocking of boron and phosphorus transient enhanced diffusion as well as retention of channel boron profiles during the gate oxidation process. The enhanced doping profile control capability is applicable to punch-through stop of advanced CMOS devices and its benefits to 28nm planar CMOS and 20nm bulk FinFET devices projected by TCAD...
Transition from planar MOSFETs to FinFETs enabled scaling beyond 28nm node. At 5nm/3nm design rules, a transition from FinFETs to nanowires has to be evaluated. We explore with rigorous NEGF (Non-Equilibrium Green's Functions) and sub-band Boltzmann transport models the impact of nanowire shape and SiGe/Si cladding layers on its performance and variability. Outside of the nanowire channel, a “bottleneck”...
A comprehensive and rigorous computational study at atomic level was performed for various vertical tunneling field-effect transistor (VTFET) structures based on III-V and two-dimensional (2D) materials. The key challenges of VTFETs were found to be induced by device structures and the channel materials' properties. An optimized VTFET structure was proposed to suppress the parasitic tunneling current...
Energy performance of nonvolatile power-gating (NVPG) that is a power-gating technique with nonvolatile state/data retention is demonstrated for nonvolatile SRAM (NV-SRAM) with spintronics retention and silicon-on-thin-BOX (SOTB) CMOS technologies. The NV-SRAM cell consists of an ordinary 6T cell and two magnetic tunnel junctions (for nonvolatile retention) with two pass-transistors. The cell and...
The SOI floating body effect and to keep floating on both the N layer and the body are important for appearance of the super steep SS on the PN-Body tied SOI FET. It was confirmed for the first time with measuring the new test devices.
We will present the current performance of the state-of-art EUV scanners, and an overview of EUV lithography process infrastructure status. The outlook for high volume manufacturing insertion will be also discussed.
Electrochemical doping, which introduces dopant impurities via isotropic electrochemical reaction, was proposed and demonstrated in an archetypical oxide semiconductor TiO2. By controlling electrochemical potential of TiO2 in electrolyte, the technique successfully introduced dopants to increase the conductivity of TiO2 by ∼5 orders. The technique was also applied through micro-patterned photo resist,...
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