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Optical crosstalk is one of the main factors limiting the performance of Single-Photon Avalanche Diode (SPAD) arrays and Silicon Photomultipliers (SiPMs). In this paper, a set of crosstalk measurements on a CMOS SPAD pixel array with 50µm × 75µm pitch and 51.6% Fill Factor, designed for direct particle detection, is reported. Measurements were performed on dies with different thickness: 280µm, 50µm...
In parallel to presentations documenting the performance of state-of-the-art FDSOI CMOS devices, we discuss selected physical mechanisms and emerging device architectures enabled by FDSOI technology.
FDSOI technologies are very promising candidates for future CMOS circuits as they feature low variability, improved short channel effect and good transport characteristics. In this paper, we review the main electrical techniques and methodologies used to characterize the important MOS device parameters. First, the capacitance-voltage measurements are considered for the vertical stack characterization...
Three-dimensional (3D) field-effect transistors (FETs) such as FinFETs and nanowire FETs are device structures for extremely scaled FETs. However, the thermal properties of 3D FETs become worse than those of conventional planar MOSFETs. As a result, an increase in channel temperature during operation, which is called self-heating effects (SHEs) is prominent in nanoscale devices. In this work, 1) SHEs...
In this work we demonstrate, for the first time, the advantages of GaN HEMTs on bulk GaN substrates over similarly processed devices on Sapphire and Silicon substrates, intended for power applications, in terms of on-state and off-state operation as well as reliability, where self-heating, off-state leakage, and trapping effects are minimal. MIS-HEMTs with breakdown voltage of ∼670 V and off-state...
The contact resistance RC of “edge-contacted” metal-graphene interfaces is systematically studied. Our experiments demonstrate a reduction of contact resistance by intentional patterning of graphene to create “edge contacts”. The parameter space for different hole patterns in graphene is explored. The contact resistance is reduced from 1518 Ωµm for structures without holes to 456 Ωµm in structures...
This paper presents the design exploration of a basic cascode circuit (CAS) targeted to increase the intrinsic gain Aν of a graphene field-effect-transistor (GFET) by decreasing its output conductance go. First, the parameters of a large-signal compact-model, based on drift-diffusion carrier transport, are fit to measurements carried on 2 CVD GFETs, fabricated independently by different research groups...
The extreme resolution of CO2 gas molecules sensing, i.e., detection of single molecule, is reported. The suspended bilayer graphene beam is exploited in order to isolate the sensing part of the device from the substrate noise. Using the electrostatic force, the central part of the suspended beam is pulled-down to bottom metal electrode, which leads to two slanted graphene beams in suspension with...
We give here an overview on our results on the large-area growth of 2D transition metal dichalcogenide semiconductors MoS2, MoSe2, WSe2 using chemical vapor deposition. The growth of MoS2 on sapphire occurs epitaxially with the crystalline orientation of the MoS2 film closely matching that of the sapphire substrate, resulting in a high-quality continuous film. The use of H2S results in more control...
We demonstrate the integration of large area graphene transparent conductive electrodes in flexible amorphous silicon multispectral (MS) photodetectors (PD). These MS diodes show a bias dependent maximum of their spectral response between the ultraviolet (UV) and visual wavelength range. This ability to shift the response maximum by external bias without the use of filter-structures and the possibility...
Graphene has a number of remarkable properties which make it well suited for both transistor devices as well as for sensor devices such as humidity sensors. Previously, the humidity sensing properties of monolayer graphene on SiO2 substrates were examined - showing rapid response and recovery over a large humidity range. Further, the devices were fabricated in a CMOS compatible process which can be...
Integration of isolated LDMOS transistors in smart power process is subjected to bipolar parasitics due to multi layers constructions that are needed for high voltage operation. These parasitics need to be minimized to assure proper circuit functionality. Several approaches for parasitics reduction are suggested: DTI (Deep Trench Isolation) module optimization, NLDMOS and PLDMOS device construction...
We study the impact of quantum mechanical effects on the fin Electron-Hole Bilayer Tunnel FET (EHBTFET) considering different geometries. Through quantum simulations based on the effective mass approximation (EMA), it is found that the fin EHBTFET is affected by the corner effects at the substrate-fin interface, due to reduced electrostatic control that causes a dramatic reduction of the ON current...
This work reports the results of a layout-aware substrate modeling methodology for HVCMOS technologies. The model relies on the extraction of parasitic substrate network to simulate with circuit software parasitic lateral NPN bipolar transistors with multi-collector configuration. This allows to predict and analyze the injected substrate currents distribution through the chip and to explore different...
Interest in resorbable and biodegradable materials originates from their potential in food packaging, environmental science and ecology, but also in medicine and biotechnology. Till very recently, electronics has not been on such development paths. However, recent advancements in material science, thin processing and nanotechnology offer the prospective of high performance electronic devices which...
Tunnel FETs (TFETs) with steep subthreshold slope have been attracting much attention as building blocks for future low-power integrated circuits and CMOS technology devices. Here we report on recent advances in vertical TFETs using III–V/Si heterojunctions. These heterojunctions, which are formed by direct integration of III–V nanowires (NWs) on Si, are promising tunnel junction for achieving steep...
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