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This paper presents an energy efficiency improvement methodology based on the use of additional static biasing instead of margins during design stage. While the impact of margins used to prevent unsystematic process limitations cannot be recovered after fabrication, using biasing anticipation offers the possibility to enable the degradation recovery only when it is required. A CAD study on ARM Cortex...
We have developed a physics based model for negative capacitance (NC) FinFETs by coupling the Landau-Khalatnikov model of ferroelctric materials with the standard BSIM-CMG model of FinFET. We apply our model to thin film Y-HfO2 (yttrium-doped hafnium oxide) based NC-FinFETs designed using state of the art 22nm technology node FinFETs. Using the same ferroelectric material, we demonstrate a device...
We present the implementation and experimental verification of the first complete digital logic library based on amorphous carbon (a-C)-coated curved-cantilever nanoelectromechanical (NEM) switch technology. Experimental results for sequential gates - latches and edge-triggered D flip-flops (DFF) - and combinational circuits (NAND, AND) are reported for the first time. The capability of the fabricated...
3DVLSI is an emerging more than Moore technology. In this paper, we propose 3D design methodologies dealing with process variability. Using SPICE models and Monte Carlo simulations we show a delay partioning method for stacked circuits to reduce frequency dispersion by 30%. We also compare how the process correlation between tiers influences the design corners.
In parallel to presentations documenting the performance of state-of-the-art FDSOI CMOS devices, we discuss selected physical mechanisms and emerging device architectures enabled by FDSOI technology.
We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI module and the SiGe-last approach using only a SiGe epitaxy after the STI module. We evidence reduced layout effects in the SiGe-last integration featuring Si/SiGe bilayer. SiGe-last shows...
We demonstrate the effectiveness and limitations of critical performance elements in silicon channel bulk finFET CMOS devices featuring embedded Source/Drain (e_SD) dual epi. Further scaling of the fin width below 10nm is shown to impact both the access resistance and S/D overlap capacitances while the mobility behavior for both nMOS and pMOS devices further degrades. Epitaxial S/D regrowth options...
FDSOI technologies are very promising candidates for future CMOS circuits as they feature low variability, improved short channel effect and good transport characteristics. In this paper, we review the main electrical techniques and methodologies used to characterize the important MOS device parameters. First, the capacitance-voltage measurements are considered for the vertical stack characterization...
A detailed statistical characterization of drain current local and global variability in sub 15nm gate length Si/SiGe Trigate NW pMOSFETs is carried out. An analytical mismatch model is used to extract the main matching parameters. Our results indicate that, despite their very aggressive dimensions, such devices maintain relatively good variability performance.
Three-dimensional (3D) field-effect transistors (FETs) such as FinFETs and nanowire FETs are device structures for extremely scaled FETs. However, the thermal properties of 3D FETs become worse than those of conventional planar MOSFETs. As a result, an increase in channel temperature during operation, which is called self-heating effects (SHEs) is prominent in nanoscale devices. In this work, 1) SHEs...
The performance of the GaN-based tri-gate HEMT is investigated by 3D numerical simulations. The tri-gate concept is shown to provide normally-off operation and to effectively suppress short-channel effects (SCEs). Furthermore, it is shown from our simulations that tri-gate AlGaN/GaN HEMTs can exhibit higher breakdown voltages and operate closer to the theoretical limit for GaN devices than their planar...
The interaction between strain and border traps in short-channel InGaAs NW MOSFETs is investigated through full-quantum 3D simulations based on a k·p Hamiltonian. Traps induce a sizable degradation of the ON-current, which can be recovered through the application of a suitable strain, provided the quantization effects, which increase by scaling the NW lateral size, do not become too large.
The impact of surface roughness (SR) and phonon scattering on extremely narrow InAs-Si Nanowire TFETs is studied in this paper. The rough surface of the nanowire is generated by randomly distributing the atoms at the InAs-Si/Oxide interface according to an Ando-like exponential auto-correlation function. Phonons are atomistically treated by means of the valence-force-field method. A full-band and...
This invited paper reviews the evolution of silicon carbide power devices from the initial proposal for wide bandgap semiconductors for power electronic applications in 1979 to current commercially available devices. The potential social impact on this technology on energy savings and the environment is briefly discussed.
In this work we demonstrate, for the first time, the advantages of GaN HEMTs on bulk GaN substrates over similarly processed devices on Sapphire and Silicon substrates, intended for power applications, in terms of on-state and off-state operation as well as reliability, where self-heating, off-state leakage, and trapping effects are minimal. MIS-HEMTs with breakdown voltage of ∼670 V and off-state...
A novel sharp switching Z2-FET DGP device (Zero Impact Ionization and Zero Subthreshold Slope FET with Dual Ground Planes) relying on band modulation mechanism is presented in this paper. The device is fabricated in the most advanced FDSOI (Fully Depleted SOI) technology with Ultra-Thin Body and Buried Oxide (UTBB). The Z2-FET DGP is an upgraded version of Z2-FET. It features sharp on-switch, adjustable...
A novel boosted MOS structure with buried n-well current booster providing >2× higher drive current and low off current is experimentally demonstrated on 28 nm bulk silicon technology. TCAD analysis is performed to investigate the boosting mechanism as well as to demonstrate scalability to 7 nm FinFET technology. Constant bias applied to the booster terminal results in a gate voltage controlled...
This work presents the analog performance of strained SOI nanowires for the first time. Triple gate MOSFETs made in strained and unstrained SOI material with variable fin widths from quasi-planar transistors to nanowires with aggressively scaled fin width are compared using experimental results in the temperature range of 300K down to 10K. Intrinsic voltage gain, transconductance and output conductance...
2D materials (2Ds), in particular the 2Ds beyond graphene, have attracted considerable attention in the transistor community. While rapid progress on 2D transistors has been achieved recently, the prospects of 2D electronics is still under debate. In the present paper we discuss our view of the potential of 2D transistors for digital CMOS and for flexible electronics. We show that 2D MOSFETs show...
In this paper, we report an accurate physics-based compact model for monolayer Graphene Field-Effect Transistors (GFETs) based on the density of states (DOS) of monolayer graphene. The charge-based model computes the total current considering a branch separation between the electron and hole contributions preserving a good accuracy near the Dirac point. The effect of back-gate is included in the charge...
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