The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The globalization of Integrated Circuits (ICs) supply chain has raised security concerns on how to ensure the integrity and the trustworthiness of fabricated circuits. While existing attack and protection methods are developed for CMOS based circuits, the introduction of emerging transistors acts as a double-sided sword. The usage of emerging devices introduces new security issues which the attackers...
With decreasing size of transistors, the impact oftransient faults as well as the local and global variability of transistors increases, affecting system functions and performances. Formal verification may be used to prove that a circuit isrobust against transient and parametric faults. However, a modelincluding timing information combined with extracted electricalparameters is typically too large...
The paper describes a method of verifying sequential arithmetic circuits by adding a special type of redundancy, called "Vanishing Polynomials" and "Don't Care Polynomials". The proof of functional correctness consists in transforming the polynomial expression at the primary outputs into a unique polynomial in the primary inputs and comparing the computed...
Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using...
Approximate memory is a promising technology for emerging recognition, mining and vision applications. These applications require the processing of large volumes of data to achieve energy-efficiency with negligible accuracy loss. This paper proposes a multi-level approximate memory architecture based on data significance analysis. In this architecture, a memory array is divided into several separated...
In this study, we introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related...
Security is becoming an essential problem for integrated circuits (ICs). Various attacks, such as reverse engineering and dumping on-chip data, have been reported to undermine IC security. IEEE 1149.1, also known as JTAG, is primarily used for IC manufacturing test but inevitably provides a "backdoor" that can be exploited to attack ICs. Encryption has been used extensively as...
Physical Unclonable Functions (PUFs) use random physical variations to map input challenges to output responses in a way that is unique to each chip. PUFs are promising low cost security primitives but unreliability of outputs limits the practical applications of PUFs. This work addresses two causes of unreliability: environmental noise and device aging. To improve reliability, we constructively apply...
Functional, at-speed vectors continue to provideadded value to the testing community as circuit complexityrises. Complex defects may escape traditional scan vectors andthus often require at-speed patterns. However, generation offunctional/sequential vectors is an extremely challenging problem. Previous methods rely on formal models of the RTL or calls togate level ATPG, both of which are computationally...
3D Integration is a promising technology to continue the trend of Moore's law. However, higher density from die stacking introduces thermal challenges that require more expensive packaging and cooling solutions. An alternative integration technology is interposer-based 2.5D design, which has fewer thermal issues but adds extra interposer cost. Designers must be aware of the system-level cost benefits...
This work presents a comparative analysis of Si/Ge and GaSb/InAs heterojunction Tunnel FET (TFET)-based cellular neural networks (CNNs). TFET-based CNNs are also compared against an equivalent FinFET-based CNN. A simulation methodology is shown to project realistic estimation of TFET-CNN performance based on the measured IDS-VGS characteristics of TFETs. III-V-TFET (i.e., GaSb/InAs TFET) shows a higher...
With drastic device shrinking, low operating voltages, increasing complexities, and high speed operations, radiation-induced soft errors have posed an ever increasing reliability challenge to both combinational and sequential circuits in advanced CMOS technologies. Therefore, it is imperative to devise efficient soft error rate (SER) estimation methods, in order to evaluate the soft error vulnerabilities...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.