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For 7 series Xilinx FPGAs, this paper shows that it is risky to believe that so fundamental operation as data delay must be always implemented without wasting chip area, even when design tools are not especially guided by a developer. Against this background, two solutions are presented that allow for minimizing the area occupied by flip-flops used to delay data that comes from outside the slices...
Even though much previous work explores adapting instruction queue (IQ) and reorder buffer (ROB) sizes to application requirements, traditional IQ/ROB optimizations may be prohibitive for resource-constrained embedded systems, due to the hardware/execution time overheads. We propose low overhead, phase-based instruction window optimization to dynamically vary IQ and ROB sizes for different execution...
Parallel and monolithic 3D-integration directions offer pathways to realize 3D integrated circuits but still lead to layer-by-layer implementations. This mindset causes challenging connectivity and alignment between layers when connected in 3D, with a routing access that can be even worse than 2D-CMOS, which fundamentally limits their potential. To fully exploit the opportunities in the third dimension,...
This paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. This new architecture does not require fine-grained location of fault, and the error map is stored in non-volatile memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the...
In this study, we propose a method to overcome the main drawback in stochastic computing, low accuracy or related long computing times. Our method exploits dependency in stochastic bit streams with the aid of feedback mechanisms. Accurate (error-free) arithmetic multiplier and adder circuits are implemented. Operations are performed using both stochastic and binary inputs/outputs, binary-stochastic...
Electrostatic discharge (ESD) is a well-known problemin integrated circuits that affects its reliability, yield and cost. It is important to design ESD protection circuits that are ableto prevent ESD related yield loss [1]. In this work, a 65 nmstatic clamp with a thyristor as a delay element to extend the ontime of the clamp during the ESD event is presented. Simulationand measurement results show...
Binary Exchange Algorithm (BEA) always introduces excessive shuffle operations when mapping FFTs on vector SIMD DSPs. This can greatly restrict the overall performance. We propose a novel mod (2P-1) shuffle function and Mod-BEA algorithm (MBEA), which can halve the shuffle operation count and unify the shuffle mode. Such unified shuffle mode inspires us to propose a set of novel mod (2P-1) shuffle...
Spin-based memory devices are gaining importancedue to multiple advantages like, zero standby power, high writeendurance and fast read, write operations. Besides storage, Spin Torque Transfer (STT)-based Magnetic Tunnel Junctions (MTJs) and Racetrack Memories (RMs) are also being investigated for logic applications, especially in the context of in-memory computing and neuromorphic architectures. Despite...
In this study, we introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related...
With current tools and technology, someone who has physical access to a chip can extract the detailed layout of the integrated circuit (IC). By using advanced visual imaging techniques, reverse engineering can reveal details that are meant to be kept secret, such as a secure protocol or novel implementation that offers a competitive advantage. A promising solution to defend against reverse engineering...
Conventional 2D CMOS faces severe challenges sub-22nm nodes. The monolithic 3D (M3D) IC technology enables ultra-high density vertical connections and provides a good path for technology node scaling. Transistor-level (TR-L) monolithic 3D IC is the most advanced and fine-grained M3D IC technology. In this paper, for the first time, the detailed design as well as benefits and challenges of a silicon...
With many advantageous features such as softness and better biocompatibility, flexible electronic device is a promising technology that can enable many emerging applications. However, most of the existing applications with flexible devices are sensors and drivers, while there is nearly no utilization aiming at complex computation, because the flexible devices have lower electron mobility, simple structure,...
In this paper, we propose a cycle-accurate monitor that can efficiently detect timing violation based fault attacks. The proposed monitor detects clock or voltage manipulations by monitoring the external clock using an internal Ring Oscillator. The monitor is low cost in terms of area and power consumption and can be easily implemented using the standard cell based VLSI design flow. In addition to...
Body biasing (BB) in bulk CMOS is an important tool for circuit designers that enables dynamic modulation of device thresholds post-fabrication, thus potentially improving yields, or allowing the circuit to adapt to different power modes, such as fully active or sleep. Fully-depleted silicon-on-insulator (FDSOI) FETs, such as ultrathin body (UTB) devices, may benefit from the same effect when the...
Magnetic logic is considered as one of the alternate technologies to the existing CMOS engineering in designing digital logic circuits. In magnetic logic, the spin directions are considered as logic levels instead of electric charge used in CMOS modules. If magnetic dots are suitably arranged, antiferromagnetic and ferromagnetic coupling can be utilized to represent a digital circuit. In this paper,...
The paper presents the design and realization of a frequency synthesizer for 60-GHz wireless communication systems. Implemented with 90nm CMOS technology, the phase-locked loop based frequency synthesizer includes a high-frequency voltage-controlled oscillator (VCO), a high-speed divider, a programmable divider, a charge pump, and a frequency tripler. The programmable divider is used to offer channel-switched...
Continuous technology scaling and increased demand for computational power have introduced a paradigm shift in manycore design requirements. On the other hand, tight power budgets and limitations of voltage scaling are throttling the ability to optimally exploit the potential of these systems, leading researchers to adopt aggressive voltage scaling techniques such as Near-Threshold Computing (NTC)...
We present the first FPGA implementation of a distributed clock synchronization algorithm with sub-nanosecond skews that can tolerate arbitrary faults of individual components. Each of n nodes is equipped with its own quartz oscillator and the nodes broadcast their clock pulses to enable synchronization. The algorithm provably maintains synchronization even if fewer than n/3 nodes exhibit arbitrary...
Since the past decade Network-on-Chip has evolved as the most dominant and efficient solution in on-chip communication paradigm for multi-core systems. With the growing number of on-chip processing cores modern three dimensional NoC design is facing several challenges originating from various network performance parameters like latency, hop count etc. Scalability and network efficiency have generated...
Energy consumption has long been one of the main constraints that has guided the design of embedded processors. VLIW architectures are well-suited for this field, since they have a simpler microarchitecture and reduced energy consumption due to their static ILP exploitation. As we will show in this paper, intelligent use of the compiler allows for power gating at a finer grain (i.e., functional units,...
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