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Stochastic computing (SC) encodes data in the signal probabilities associated with pseudo-random bit-streams. It enables very low-area and low-power arithmetic operations using standard VLSI circuits, it is also highly error-tolerant. While addition, subtraction and multiplication have extremely simple SC implementations, this is not true for division. Known stochastic dividers employ sequential logic...
This paper proposes the design of an adaptive filterin stochastic circuits. The proposed circuit requires lower areaand power than a conventional stochastic implementation. In theproposed design, the stochastic multiplier is implemented by anXNOR gate, as in a conventional scheme. However, the stochasticadder based on a multiplexer is not a very efficient implementationdue to the three required stochastic...
Subthreshold ultra-low-power passive RFID tag's baseband processor core design with custom logic cells is presented in this paper, based on EPC C1G2 protocol. To deal with the critical timing and wide-range-PVT variation problems of the processor at very low power supply, and for the consideration of limited availability of RF power, power-aware scheme is applied to the key modules, including PIE...
In this paper, we propose a cycle-accurate monitor that can efficiently detect timing violation based fault attacks. The proposed monitor detects clock or voltage manipulations by monitoring the external clock using an internal Ring Oscillator. The monitor is low cost in terms of area and power consumption and can be easily implemented using the standard cell based VLSI design flow. In addition to...
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