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VeSTIC (Vertical-Slit Transistor based Integrated Circuit) architecture enables easy integration of all types of transistors on the same chip. One of the elements available in this technology is Junction Vertical-Slit Field-Effect Transistor (JVeSFET). Simulation based feasibility studies indicate that the device exhibit attractive electrical properties like DC characteristics of relatively low subthreshold...
High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach based on transistor layout is presented that is compatible with parasitic substrate noise propagation in Smart Power ICs. The results of the model...
When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our methodology consists...
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