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In this paper design of critical building blocks of a 10 GHz silicon integrated circuit of an FMCW radar transceiver is reported. Specifically, design of VCO and LNA is discussed. The targeted transceiver structure will be world's first, commercially available silicon integrated circuit built in SiGe BiCMOS technology and dedicated for low-power radar applications.
In this paper a comparison of four low noise amplifiers (LNAs), designed in fully depleted SOI 28 nm technology, has been presented. The objective of the presented work was to verify the usability of all kinds of MOSFET transistors that are available in UTBB for RF analog designs. The inductively degenerated cascodes were used in simulations. Such topology achieves high gain and low noise figure (NF)...
A wideband CMOS receiver front-end for radio applications operating between 300 MHz and 900 MHz is presented. In order to obtain channel selection with image-rejection and out-of-band interferers attenuation, both low-noise amplifier (LNA) and mixer incorporate a N-Path signal processing technique. The effectiveness of this N-Path filtering is investigated by comparing distinct combinations of clock...
In this paper, we provide a detailed analysis on the power consumption of two-stage pipeline successive approximation analog-to-digital converter (SAR ADC) and also show the relationship between stage resolution and the total power consumption in 65 nm technology. Thereafter, we evaluate the analysis results with designing a 15-bit pipeline SAR ADC in 65 nm technology and also a power comparison between...
This paper presents a class-D power amplifier for medium quality sound systems using a second-order passive sigma-delta modulator (ΣΔM). The ΣΔM controls an output power stage consisting of a H-bridge. The loop filter of the ΣΔM was designed using a optimization procedure based on genetic algorithm (GA), that takes into account several parameters. This system was implemented using discrete components...
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