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Network on Chip (NoC) is a new paradigm to address the challenges of System on Chip design. In this paper, we present a fast multi-core virtual platform which integrates OVP processor model, TLM-2.0 and NoC, to evaluate the system performance. We develop a unicast network with mesh topology and a multicast network with ring topology. In addition, Data Encryption Standard (DES) algorithm is implemented...
This paper presents a light-emitting diode (LED) driver for general lighting applications. In addition to providing a high stable current source for the LED biasing, the new circuit provides an energy-efficient way for light intensity control using a pulse width modulation (PWM)-based dimming circuit. Moreover, we introduce a feedback thermal control circuit to ensure the LED being operated at a temperature...
A new true-single-phase clocked (TSPC) full-adder using floating-gate MOS (FGMOS) transistor is presented. In this new design scheme, the logic tree for the sum-generate circuit is realized using only an n-channel multiple-input FGMOS transistor, and the logic for the carry-generate circuit is realized using a complementary FGMOS-based inverter. By using FGMOS transistors, the circuit structure can...
This paper describes a 0.18µm CMOS switched-capacitor 2-1 cascade sigma delta modulator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The modulator occupies an area of 0.14 mm2 and dissipates 9.9 mW from 3.3 V supply. The modulator clocked at 10 MHz and considering 4 kHz...
A multi-level 2D-IDWT's architecture with high performance and memory efficiency is proposed. The proposed architecture is composed of two 1D-IDWT cores and one single rearrangement register. Both the 1D-IDWT cores take only one multiplier delay in their critical path at the throughput rate of one-input/one-output. The single register, rather than traditional 1.5N transposing memory, is used to complete...
Cobalt-based amorphous ribbons (Metglas® 2714A) were annealed treatment with an applied magnetic field. During annealing, the angle between the magnetic field axis and ribbon axis was designed for 0°, 30°, 60° and 90° respectively. MEMS technology was used to fabricate micro-patterned Co-based amorphous ribbons with a meander structure. The giant magnetoimpedance (GMI) effects were observed. The results...
First-principle calculations were performed to investigate the resistance of nickel-ZGNRs(with H-terminated or bare edges) junctions. The edge modification contributes to reduce the resistance of the contact and causes the the negative resistance effect to disappear in our investigations.
In the paper, the EIS structure with high-k CeO2 sensing film has more responsive to H+ relative to Na+ and K+. The CeO2 sensing membrane annealed with O2 at 800°C shows a higher sensitivity of 58.76 mV/pH, higher linearity, lower hysteresis voltage of 5.97 mV and lower drift rate of 0.96 mV/hr than the other conditions.
Fermi level pinning at the Ge valence band results in a high schottky barrier height (SBH) for all metal/n-Ge contacts. In this work, by inserting an ultrathin insulator between metal and germanium, the SBH of Al/Ge can be reduced from 0.6 eV to about 0.3eV. Barrier height reduction was measured and compared for several inserted insulators. This structure has application as a low resistance ohmic...
This paper presents the design of a digitally controlled oscillator for low voltage energy harvesters without external components. The performance of the oscillator is verified with simulation results in CSMC 180nm CMOS process. The oscillator operates at a frequency range from 16.5kHz to 82KHz and consumes 85nW at a 1V supply voltage and room temperature, and a temperature coefficient about 172 ppm/°C...
Fourier transform is the basic operation between time and frequency domain transformation. As a key operation of digital signal processing system, Fast Fourier Transform (FFT) is widely used in many fields such as communication, biomedical signal processing and image processing, which require a high precision of processed signal. To meet the requirement, the floating point number can be used to improve...
Based on a standard 0.18µm CMOS technology, a novel four-stage fully-differential ring voltage-controlled oscillator (VCO) with high speed, low power and a wide tuning range is proposed. The inductive shunt peaking technique with active inductors is employed to expand the bandwidth of the delay cell, and a pair of PMOS transistors with gates connected to the ground is added to to increase the oscillation...
A novel digital programmable gain amplifier (PGA) is proposed in this paper. The proposed design avoids the gain accuracy affected by on-resistance of control switches, leading to much more accurate gain. The cor-responding algorithm is shown in this paper. The circuits are implemented in CSMC 0.35 µm Technology. When the gain is from 0dB to 20dB, step is 2dB; from 0dB to −20dB, step is 20dB. It is...
This paper proposed a Mixed-Voltage Bidirectional (MVB) I/O IP core for an automotive Body Control Module (BCM) SoC. It is based on a conventional bidirectional I/O circuit, four configuration signals with a constraints module, and level shifters to transform 1.8V core logic to 3.3V or 5V external logic are added. Data level shifter and input Schmitt trigger are modified to achieve low power strategy...
Low Voltage Power line communication (LV-PLC) systems have the disadvantage of poor channel condition, since power lines are not designed for data transmission. Due to the complex and time variance characteristics in LV-PLC systems, people shall pay more attentions on the adaptive modulation technique in OFDM systems. In this paper, we built an OFDM system model with PLC channel model and noise environment...
Low-power and small-area implementations are essential in the CMOS image sensor market. At the same time, to achieve high-accuracy and high-speed is very important for ADC studying. This paper presents the design of a 10-bit 20MS/s differential Successive Approximation Register (SAR) ADC with a new switching procedure using for CMOS image sensor application. Compared with conventional 10-bit ADC,...
Parallelism of Montgomery modular multiplication (MM) in residue number system (RNS) is exploited on NoC-based platform in this paper. First, the state of the art MM algorithm is studied. Then, the influence of communication latency is discussed, and the parallelism is exploited base on several aspects of the parallelism. An efficient parallelization scheme is proposed to overcome the influence caused...
Bank IC cards are now widely used all over the world, particularly in Europe and Asia, and in the meantime facing serious security problems. To protect bus in the bank IC card against attacks, a novel bus security solution including two methods are proposed in this paper to protect AMBA (Advanced Microcontroller Bus Architecture), which is used for interconnection between the 32-bit CPU and memories...
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The proposed design technique is applied to a divide-by-2/3 unit, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 49% reduction of PDP is achieved by the proposed unit.
This paper proposes a PCM hybrid main memory management scheme called APABL (Adaptive PRAM aware Block-based LRU). Proposed scheme takes DRAM as the first memory and PCM as the spare memory. Only data evicted from DRAM is to be written into PCM. Our scheme can reduce both the access times to PCM and SSD without performance loss. Thus, it can also benefit the mobile computer.
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