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The superior gate stack was fabricated by employing novel high vacuum annealing followed by in-situ metal capping method to suppress GeOx regrowth. Less GeO volatilization induces less Ta diffusion into gate oxide which reduces leakage current and enables further scaling. With ZrO2/Zr-cap stack, highly scaled Ge (100) pMOSFETs have been demonstrated which shows extremely low EOT (6.06 Å), low gate...
Carbon nanotube (CNT) non-volatile memory provides excellent cell characteristics of >1011 endurance, low power, fast <5ns array program, and multi-level cell (MLC) potential. For the first time, optimal program methods are investigated considering speed, power and cell variability. Discrete cells are measured and a multiple-pulse reset scheme is proposed to reduce verify-reset time and a gate...
For the first time, we report a spatial mapping methodology to directly obtain spatial BD distributions from TDDB data at wafer-scales. The results reveal BD defects are strongly clustered towards later stress times and explain the root-cause of non-Poisson area-scaling in agreement with recently developed time-dependent clustering model [3,4]. This methodology provides important detailed information...
Fin-based analog, passive, RF and ESD devices have serious performance challenges, such as poor ideality, higher leakage, low breakdown voltage (BV) of diodes, BJTs with poor ideality, mismatch, weak re-surf action and low drain current(Id/µm) of Laterally diffused MOS (LDMOS), degraded RF and 1/f noise of analog CMOS, etc. Innovative solutions which maintain process simplicity and low cost are described...
Super Jg-EOT gate stack characteristics, ultra-high κ value, and the promising transistor's performance are achieved on the Ge n-FET by the application of the BaTiO3 as the gate dielectric and the magnetic FePt film as the metal gate. The super Cgate/κ-value is generated by more dipoles in the HK dielectric layer with the coupling of the build-in magnetic field from MG (HK: BaTiO3; MG: magnetic FePt)...
We report a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). Both junctionless (JL) nFETs and pFETs are integrated on a common GeOI substrate. The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current (Imax) of 714 mA/mm and trans-conductance (gmax) of 590 mS/mm, high Ion/Ioff ratio of 1×105 are archived at...
Hybrid memory systems that incorporate Storage Class Memory (SCM) as non-volatile cache or DRAM data backup are expected to bolster system efficiency and cost because SCM promises higher density than DRAM cache and higher speed than the storage I/F. This paper demonstrates a Cu-based resistive random access memory (ReRAM) cell that meets the SCM performance specifications for a 16Gb ReRAM with 200MB/s...
InxGa1−xAs FinFETs with varying indium percentage, x, and vertical body thicknesses, are fabricated in a closely packed fin configuration (10 fins per micron of layout area) and their relative performance analyzed and benchmarked. In0.7Ga0.3As quantum well FinFET (QWFF) exhibits peak field effect mobility of 3,000 cm2/V-sec at a fin width of 38nm with highest performance. Short channel In0.7Ga0.3As...
Novel nonvolatile programmable switch for low-power and high-speed FPGA where MONOS flash is adjacently integrated to CMOS logic is demonstrated. The MONOS transistors (MTrs.) and low-voltage switching transistors (SwTrs.) are fabricated close to each other without deteriorating each performance. Furthermore, memory programming scheme is optimized to realize selective writing with no damage in the...
This paper reports on gate-last (GL) In0.7Ga0.3As QW MOSFETs with regrown S/D by MOCVD. Long-channel devices exhibit excellent electrostatics and carrier transport (SS=80mV/dec., DIBL=22mV/V, and μn,eff>5,500 cm2/V-s at 300k). Short-channel device with Lg = 40 nm also exhibit excellent electrostatic integrity of SS = 105 mV/dec., and DIBL = 150 mV/V, together with gm_max = 2 mS/µm at VDS = 0.5...
Various product applications bring up with increasing demands of logic NVM IP in advanced technology nodes. Encryption, security, functionality, and identification setting become indispensable in communication and high-end consumer electronics. A non-volatile memory cell, using anti-fuse programming mechanism to achieve high density and excellent data storage lifetime, is proposed. The unique cell...
A Vth self-adjusting MOSFET consisting of floating gate is proposed and the ultra-low voltage operation of the Vth self-adjustment and SRAM cell at as low as 0.1V is successfully demonstrated. In this device, Vth automatically decreases at on-state and increases at off-state, resulting in high Ion/Ioff ratio as well as stable SRAM operation at low Vdd. The minimum operation voltage at 0.1V is experimentally...
This paper summarizes key learnings on 20/16nm CPI (Chip-Package-Interaction) challenges at 100um pitch and below to support ever increasing performance/cost/form factor demands for high performance mobile SoCs. CPI solutions for two types of Cu pillar interconnects using mass reflow and thermal compression type assembly process respectively are studied in technology development/production, and separate...
We first achieved ultra-low NiGe specific contact resistivities (ρc's) of 2.3×10−9Ωcm2 and 1.9×10−8Ωcm2, which were both reduced from the best values ever reported by one order of magnitude, for Ge P- and N-MOS, respectively. The keys to the excellent performance were carrier activation enhancement (CAE) techniques using Ge pre-amorphization implant (PAI) or laser anneal (LA) followed by an in-situ...
3D RRAM array suffers more serious reliability issues than 2D array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3D vertical RRAM array. Using a combination of experiments and simulations, a methodology is developed to enable array-level evaluation by conducting...
We demonstrate a selector device with excellent performances (JMAX > 107A/cm2, switching speed < 20ns) at the 30nm cell size. Furthermore, these promising device characteristics were achieved in a fully CMOS compatible stack (W/Ta2O5/TaOx/TiO2/TiN) with extremely thin oxide layer (< 10nm). Through the comprehensive understanding on the exponential I–V curve, the effect of intrinsic/extrinsic...
The first demonstration of Germanium-Tin on Silicon (Ge1−χSnχ/Si) avalanche photodiode (APD) for short-wave infrared (SWIR) imaging is reported. The temperature dependence of breakdown voltage was characterized. An extracted thermal coefficient of 0.05% K−1 indicates that the Ge1−χSnχ/Si APD achieved a lower thermal sensitivity than conventional III–V-based APDs. At the wavelength λ of 1600 to 1630...
A novel helium-3 ion bombardment technique is proposed for creating locally semi-insulating substrate areas. A helium-3 dose of only 1.5×1013cm−2 increases a Si substrate resistivity from 6Ω-cm to 1.5kΩ-cm, which improves the quality factor of a 2-nH inductor with a 140µm-diameter by 38% (Q=16.3). An aluminum mask is used for covering active areas, and at most 15-µm distance from the mask edge is...
We present a systematic investigation of the impact of aggressive lateral and vertical TiN/Hf(Al)O/Hf/TiN RRAM cells stack scaling down to 10nmx10nm cell size and 5nm thickness on performance and reliability. We demonstrate that median values and 1-sigma dispersion of programming voltages, resistances and disturb are not affected by lateral and vertical scaling in agreement with QPC/hour glass conduction...
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