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In this paper we describe the development of integrated lateral thyristors in NXP's proprietary HV-SOI technology [1]. Thyristors are typically used for their extreme high-current capability or their zero-crossing switch-off, that allow easy implementation of phase-controlled power conversion. In this work, the main motivation to select thyristors is their ability to operate as an efficient switch...
We report our development of a novel NLDMOS in SOI based smart power technology, integrated into Freescale's 0.13μm CMOS platform. The new NLDMOS not only achieves BVDSS up to 140V in both low side and high side operations, but more importantly, the Rdson∗Area is able to shrink at least 35–40% below the current benchmark, which is the lowest reported for BVDSS ranging from 50V to 138V. For the first...
Advanced 0.16 μm BCD technology platform offering dense logic transistors (1.8 V-5 V CMOS) and high performance analog features has been developed. Thanks to dedicated field plate optimization, body and drain engineering, state of the art power devices (8 V to 42 V rated) have been obtained ensuring large Safe Operating Areas with best RONXAREA-BVDSS tradeoff.
This paper presents complimentary 85V-rated LDMOS devices integrated in a 180nm power management technology platform. The devices are fabricated using a design technique which utilizes tapered dielectric regions in combination with patterned floating field plated structures. The performance of the new structures are compared to conventional LDMOS structures and it shown that the floating field plated...
A new TCAD-based approach is used to investigate hot-carrier stress (HCS) effects, especially suited for power devices. Physically-based degradation models are used to determine the interface trap generation at different stress biases and ambient temperatures. Special attention has been given to the high current-voltage regimes, when significant self-heating effects and impact ionization play a relevant...
This paper describes anomalous shifts of an off-state I-V curve that are found in an STI-based LD-PMOS, which includes degradation and recovery of breakdown voltage, increase in leakage current, and subsequent destruction under HCI stressing. Our experimental results suggest that the degradation and the recovery are caused by hot electrons injected into the STI around the bottom corner and the top...
MR-DCIV current has demonstrated the nondestructive capability to profile the interface states along the channel, accumulation and STI regions in high-voltage LDMOSFET. The correlation between interface state and MR-DCIV current has been studied under high voltage stresses in LDMOSFETs. Our study results show that RON degradation is mainly affected by newly-generated interface states in the STI region...
A 200V lateral insulated gate bipolar transistor (LIGBT) was successfully developed using lateral superjunction (SJ) in 0.18μm partial silicon on insulator (SOI) HV process. The results presented are based on extensive experimental measurements and numerical simulations. For an n-type lateral SJ LIGBT, the p layer in the SJ drift region helps in achieving uniform electric field distribution. Furthermore,...
The reliability of high performance Field-PMOS FET with thick gate oxide was improved. By reducing the amount of charge in the insulating film, RESURF effect was well performed in the drift region to obtain BVDSS over 350 V. Gate oxide breakdown voltage was found to decreas at AC high slew rate, and its reduction was suppressed with the fluorine termination. NBTI shift was also reduced within 15 %...
Integrated in a 0.35 μm 700 V BCD process platform, ultra-low Ron, sp 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which Ron, sp are 11.5 Ω·mm2 and 11.2 Ω·mm2, respectively. Utra-low Ron, sp benefits from optimized device size and strict limitations for annealing temperature...
An 800V rated lateral IGBT for high frequency, low-cost off-line applications has been developed. The LIGBT features a new method of adjusting the bipolar gain, based on a floating N+ stripe in front of the P+ anode/drain region. The floating N+ layer enhances the carrier recombination at the anode/drain side of the drift region resulting in a very significant decrease in the turn-off speed and substantially...
High-voltage AlGaN/GaN HEMTs fabricated on a GaN-on-SOI platform were demonstrated. The GaN-on-SOI wafer features III-nitride epi-layers grown by MOCVD on a modified SOI wafer consisting of a p-type (111) Si device layer, a SiO2 buried oxide and a p-type (100) Si handle substrate. Depletion- and enhancementmode HEMTs are monolithically integrated. The Enhancement-mode HEMTs obtained by fluorine plasma...
In this paper, we present a method of reducing threshold voltage shift for normally-off GaN MIS-HEMT by the optimization of dielectric deposition conditions. High-temperature deposition of Al2O3 insulator decreases the impurities in a dielectric film, leading to small C-V and I-V hysteresis under large positive gate voltage operation. Moreover, Al2O3 deposited at high temperature achieve high quality...
Heavily doped GaN nanochannel FinFET has been proposed and fabricated, for the first time, which does not have any p-n junction or heterojunction. In spite of its easy and simple epitaxial growth and fabrication process, the fabricated device with nanochannel width of 80 nm and gate length of 1 μm exhibited excellent off-state performances such as extremely low off-state leakage current of ∼ 10−11...
We find that off-state breakdown in AlGaN/GaN insulated-gate HEMTs can occur at the source-side of the gate with increase in the drain voltage. This new finding is borne out by extensive electrical measurements and confirmed with the OBIRCH (Optical Beam Induced Resistance CHange) technique. It is explained by a hypothesis whereby holes generated at high Vds flow to the source-side of the gate, and...
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