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Qucs and QucsStudio open source circuit simulators have a wealth of built in swept data features, including facilities for linear and logarithmic scans of simulation variables and for setting component values and device parameters. These simulators also allow semicolon separated lists of numerical values to be used as swept data. This little known feature provides a very flexible mechanism for generating...
In this paper an approach to analysis of responsivity of MOSFET-based detectors of THz radiation has been presented. The author has analyzed the substrate modes that affect performance of antennas that are always used as a part of detecting structures, and should be accounted for by proper choice of the substrate geometry. Then, a methodology to combine extracted properties of an arbitrary antenna...
In this article, an analog fully programmable membership function generator (MFG) is presented. It is capable of generating Gaussian, Triangular and Trapezoidal shapes as well as S or Z shapes. For omitting noise disturbances, differential structures are utilized in input and output stages which are in voltage mode and current mode, respectively. In contrast with conventional MFGs which are controlled...
A novel high speed and tunable transconductor suitable for analog and mixed-signal fuzzy circuits operating in current mode and a high linear MIN circuit are proposed. Using this OTA, we construct are high speed Gaussian and trapezoidal-shaped fuzzifier and implement S-shaped and Z-shaped function with all parameters (slop, width, and position) independently and continuously tunable, and excellent...
This paper presents design approaches focused on application of amplifiers structures in High-voltage technology processes with special regards to Silicon-on-Insulator ones. Voltage-mode and current-mode approaches are taken into account and implemented. The presented topologies are discussed and HV application potential of current-mode is pointed out.
The paper presents a VHDL-AMS based approach to the Switched-Current (SI) Sigma-Delta Modulator design. EDA tools are presented, which translate the prototype VHDL-AMS description into SI realization. Another tool helps the designer to create the layout. The paper also describes a new proposed current mode comparator, which is used in the design. Postlayout simulation results are presented.
This paper presents a new high speed, low power 5-2 compressor which is constructed according to a sensible combination of pass transistor logics and static logics. The 5-2 compressor is designed based on a new truth table that is obtained by performing some changes on its conventional truth table. So simple structures are obtained in which capacitances of middle stages are decreased. Therefore, a...
This paper presents a simple circuit technique to reduce gain variability with temperature in cascode amplifiers using a body-biasing scheme, and at the same time, enhance the overall gain of the amplifier. Simulation results of a standard telescopic-cascode amplifier, in two different nanoscale CMOS technologies (130 nm and 65 nm) show that it is possible to obtain supply-and-temperature-compensation...
While software detecting plagiarism in text or computer code is commonly used these days, no counterpart exists for integrated-circuit (IC) layouts. This paper proposes several criteria of IC-layout dissimilarity that can be used for computer-aided layouts matching. A program based on these criteria is shown to successfully identify similar layouts in a pool of designs.
The design and measurements results of analog-to-digital converter implemented in CMOS 180 nm technology have been presented in this paper. The successive approximation architecture with charge redistribution has been chosen. Much emphasis was placed on limiting the area occupancy of the whole chip so as its power consumption, which makes the described circuit suitable for multichannel applications...
This paper describes design of readout circuit destined for NMOS terahertz detectors. The proposed architecture bases on chopper amplifier and instrumentation amplifier concepts. The main goals were to achieve high gain (max. 100 dB) and to enable proper operation with NMOS-based THz detector. For the research needs three different architectures of chopper amplifier have been developed. The designed...
This paper presents a dual stage charge-sensitive amplifier designed for long silicon strip detectors. It allows to obtain a linear Time-over-Threshold processing using constant current feedback for charge and interaction time measurements when working with large capacitance sensors (e.g. Cdet=30 pF). The paper includes details of architecture and simulation results.
A new technique to enhance single-stage operational transconductance amplifiers (OTAs) is presented. Enhanced DC gain and reduced input parasitic capacitances are achieved by employing two input fully-differential voltage combiners, i.e. a combination of transistors in common-drain and common-source configurations operating as a preamplifier stage. Simulation results show that the input capacitance...
This paper presents ways of enable and power-down functionality implementation in HV SoI buffers. Several HV buffer topologies are taken into account. Power-down, high input and output impedance functionality implementation approaches are presented and discussed.
We present a design and simulation results of an integrated circuit dedicated to recording and detection of a broad range of biomedical signals. The chip is designed in a 180nm CMOS technology and occupies 1.5×1.5 mm2. It consists of 8 channels responsible for amplification, filtration, and detection of biomedical signals. Main parameters of the single recording channel such as a voltage gain, frequency...
In this paper a new approach for technology migration of analogue CMOS circuits is presented. The Hooke-Jeeves algorithm and genetic algorithms, are considered for multi criteria optimization in conjunction with HSPICE simulation software. Their goal is to calculate the values for circuits' elements for implementation in certain technology of fabrication. The modifications and improvements introduced...
This paper presents results of analyses of full adders structures to build of low-power adders for specific data. At first four 1-bit full adder cells were selected from literature, designed in UMC 180nm technology and simulated for assessment of theirs energetic and time parameters. Extended power consumption model, taking into consideration input vector changes, was used, giving more accurate values...
This paper presents the effect SOI detector's bias voltage has on current-voltage characteristics of different types of transistors (core transistors, io transistors, body floating, sourcetie, body-tie, low/normal/high threshold voltage). Methods of minimizing this effect were presented. Also, the I–V characteristic of transistors utilizing shielding layer (BPW - buried P Well) were measured and presented...
In this paper it is presented a balun LNA, with voltage gain control that combines a common-gate and common-source stage, in which transistors biased in triode region replace the resistive loads. This last approach in conjunction with a dynamic threshold reduction technique allows a low supply voltage operation. Furthermore, a significant chip area reduction can be exploited by adopting an inductor-less...
A laboratory setup for investigation of maximum power point trackers (MPPT) for photovoltaic (PV) modules is presented. It is composed of a PV module, an artificial light source and a universal maximum MPPT circuit. The PV module has been customised so that to enable investigation of partial shadowing effects and related countermeasures. Halogen lamps provide a constant irradiation and pulse operation...
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